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? freescale semiconductor, inc., 2000, 2001 , 2002, 2003, 2004, 2005, 2006, 2007. all rights reserved. freescale semiconductor data sheet: technical data this document contains information on a new product. specificatio ns and information herein are su bject to change without notice . document number: DSP56366 rev. 3.1, 1/2007 1 overview the DSP56366 supports digita l audio applications requiring sound field processi ng, acoustic equalization, and other digital audio al gorithms. the DSP56366 uses the high performance, sing le-clock-per-cycle dsp56300 core family of programma ble cmos digital signal processors (dsps) combined with the audio signal processing capability of the freescale symphony? dsp family, as shown in figure 1-1 . this design provides a two-fold performance incr ease over freescale?s popular 56000 symphony family of dsps while retaining code compatibility. significant ar chitectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct memo ry access (dma). the DSP56366 offers 120 million instructions per second (mips) using an intern al 120 mhz clock at 3.3 v. DSP56366 24-bit audio digital signal processor contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 signal/connection descriptions . . . . . . . . . 2-1 3 specifications . . . . . . . . . . . . . . . . . . . . . . . . 3-1 4 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 5 design considerations . . . . . . . . . . . . . . . . 5-1 6 ordering information . . . . . . . . . . . . . . . . . . 6-1 a power consumption benchmark . . . . . . . . a-1
overview DSP56366 technical data, rev. 3.1 1-2 freescale semiconductor figure 1-1 DSP56366 block diagram data sheet conventions this data sheet uses the following conventions: overbar used to indicate a si gnal that is active when pulled low (for example, the reset pin is active when low.) ?asserted? means that a high true (active high) signal is high or that a low true (active low) signal is low ?deasserted? means that a high true (active high) signal is low or that a low true (active low) signal is high examples: signal/symbol logic state signal state voltage* pin true asserted v il / v ol pin false deasserted v ih / v oh pin true asserted v ih / v oh pin false deasserted v il / v ol note: *values for v il , v ol , v ih , and v oh are defined by individual product specifications. clock generator internal data bus switch extal program interrupt controller program decode control ler program address generator ya b xab pa b ydb xdb pdb gdb moda/irqa modb/irqb data alu 24x24 + 56 -> 56-bit mac two 56-bit accumulators barrel shifter modc/irqc pll once? host inter- face dax (spdif tx.) inter- face 4 16 x memory ram 13k x 24 rom 32k x 24 y memory ram 7k x 24 rom 8k x 24 ddb dab six channels dma unit memory expansion area peripheral ym_eb xm_eb pm_eb pio_eb 24 bits bus expansion area jtag 4 5 reset power mngmnt pinit/nmi 2 triple timer 1 modd/irqd dram & sram bus interface & i - cache external address bus switch external data bus switch address 10 data control 24 18 esai inter- face 8 6 esai_1 address generation unit 24-bit dsp56300 core shi inter- face program ram/instr. cache 3k x 24 program rom 40k x 24 bootstrap rom 192 x 24
overview DSP56366 technical data, rev. 3.1 freescale semiconductor 1-3 1.1 features 1.1.1 dsp56300 modular chassis ? 120 million instructions per second (m ips) with an 120 mhz clock at 3.3v. ? object code compatible with the 56k core. ? data alu with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shif ter. 16-bit arithmetic support. ? program control with posit ion independent code support and instruction cache support. ? six-channel dma controller. ? pll based clocking with a wide ra nge of frequency multiplications (1 to 4096), predivider factors (1 to 16) and power saving clock divider (2 i : i=0 to 7). reduces clock noise. ? internal address tracing support and once ? for hardware/software debugging. ? jtag port. ? very low-power cmos design, fu lly static design with opera ting frequencies down to dc. ? stop and wait low-power standby modes. 1.1.2 on-chip memory configuration ? 7kx24 bit y-data ram and 8kx24 bit y-data rom. ? 13kx24 bit x-data ram a nd 32kx24 bit x-data rom. ? 40kx24 bit program rom. ? 3kx24 bit program ram and 192x24 bit bootstrap rom. 1k of program ram may be used as instruction cache or fo r program rom patching. ? 2kx24 bit from y data ram and 5kx24 bit from x data ram can be switched to program ram resulting in up to 10kx24 bit of program ram. 1.1.3 off-chip memory expansion ? external memory expansion port. ? off-chip expansion up to two 16m x 24-bit word of data memory. ? off-chip expansion up to 16m x 24-bit word of program memory. ? simultaneous glueless in terface to sram and dram. 1.1.4 peripheral modules ? serial audio interface (esai): up to 4 receivers and up to 6 tran smitters, master or slave. i 2 s, sony, ac97, network and other programmable protocols. ? serial audio interface i(esai_1): up to 4 receivers and up to 6 transmitters, master or slave. i 2 s, sony, ac97, network and othe r programmable protocols the esai_1 shares four of the data pins w ith esai, and esai_1 doe s not support hckr and hckt (high frequency clocks)
overview DSP56366 technical data, rev. 3.1 1-4 freescale semiconductor ? serial host interfa ce (shi): spi and i 2 c protocols, multi ma ster capability, 10- word receive fifo, support for 8, 16 and 24-bit words. ? byte-wide parallel host in terface (hdi08) w ith dma support. ? triple timer module (tec). ? digital audio transmitter (dax): 1 serial tr ansmitter capable of supporting the spdif, iec958, cp-340 and aes/ebu digital audio formats. ? pins of unused peripherals (except sh i) may be programmed as gpio lines. 1.1.5 packaging ? 144-pin plastic lqfp package. 1.2 documentation table 1-1 lists the documents that provide a complete description of the DSP56366 and are required to design properly with the part. docume ntation is available from a local freescale distributor, a freescale semiconductor sales office, a freescal e literature distributi on center, or through the freescale dsp home page on the internet (the sour ce for the latest information). table 1-1 DSP56366 documentation document name description order number dsp56300 family manual detailed description of the 56300-family architecture and the 24-bit core processor and instruction set dsp56300fm DSP56366 user?s manual detailed description of memory, peripherals, and interfaces DSP56366um DSP56366 product brief brief description of the chip DSP56366p DSP56366 technical data sheet (this document) electrical and timing specifications; pin and package descriptions DSP56366 ibis model input output buffer information specification. for software or simulation models, contact sales or go to www.freescale.com.
DSP56366 technical data, rev. 3.1 freescale semiconductor 2-1 2 signal/connection descriptions 2.1 signal groupings the input and output signals of th e DSP56366 are organized into functi onal groups, which are listed in table 2-1 and illustrated in figure 2-1 . the DSP56366 is operated from a 3.3 v supply; however, some of the inputs can tolerate 5 v. a special notice for this feature is added to th e signal descriptions of those inputs. table 2-1 DSP56366 functional signal groupings functional group number of signals detailed description power (v cc )20 table 2-2 ground (gnd) 18 table 2-3 clock and pll 3 table 2-4 address bus port a 1 1 port a is the external memory interface port, including the external address bus, data bus, and control signals. 18 table 2-5 data bus 24 table 2-6 bus control 10 table 2-7 interrupt and mode control 5 table 2-8 hdi08 port b 2 2 port b signals are the gpio port signals which are multiplexed with the hdi08 signals. 16 table 2-9 shi 5 table 2-10 esai port c 3 3 port c signals are the gpio port signals which are multiplexed with the esai signals. 12 table 2-11 esai_1 port e 4 4 port e signals are the gpio port signals wh ich are multiplexed with the esai_1 signals. 6 table 2-12 digital audio transmitter (dax) port d 5 5 port d signals are the gpio port signals which are multiplexed with the dax signals. 2 table 2-13 timer 1 table 2-14 jtag/once port 4 table 2-15
DSP56366 technical data, rev. 3.1 2-2 freescale semiconductor figure 2-1 signals identified by functional group port a address bus a0-a17 vcca (3) gnda (4) d0-d23 vccd (4) gndd (4) aa0-aa2/ras0 -ras2 port a bus control port a data bus once ? on-chip emulation/ tck tdo vcch gndh vccql (4) port b port c jtag port pinit/nmi vccqh (3) vccc (2) gndc (2) interrupt and mode control moda/irqa modb/irqb modc/irqc modd/irqd reset pll and clock extal pcap gndp vccp port d quiet power gndq (4) spdif transmitter (dax) ado [pd1] aci [pd0] timer 0 tio0 [tio0] hreq sck/scl miso/sda ss /ha2 mosi/ha0 tms parallel host port (hdi08) DSP56366 had(7:0) [pb0-pb7] has/ha0 [pb8] ha8/ha1 [pb9] ha9/ha2 [pb10] hrw/hrd [pb11] hds/hwr [pb12] hcs/ha10 [pb13] horeq/htrq [pb14] hack/hrrq [pb15] serial audio interface (esai) tdi serial host interface (shi) gnds (2) vccs (2) fst [pc4] hckt [pc5] sckr [pc0] fsr [pc1] hckr [pc2] sdo0[pc11] / sdo0_1[pe11] sdo1[pc10] / sdo1_1[pe10] sdo2/sdi3[pc9] / sdo2_1/sdi3_1[pe9] sdo3/sdi2[pc8] / sdo3_1/sdi2_1[pe8] sdo4/sdi1 [pc7] sdo5/sdi0 [pc6] fs sckt_1[pe3] sckt[pc3] t_1[pe4] sckr_1[pe0] fsr_1[pe1] sdo4_1/sdi1_1[pe7] sdo5_1/sdi0_1[pe6] bb bg br ta wr rd cas port e serial audio interface(esai_1)
DSP56366 technical data, rev. 3.1 freescale semiconductor 2-3 2.2 power 2.3 ground table 2-2 power inputs power name description v ccp pll power ?v ccp is v cc dedicated for pll use. the voltage should be well-regulated and the input should be provided with an extremely low impedance path to the v cc power rail. there is one v ccp input. v ccql (4) quiet core (low) power? v ccql is an isolated power for the internal processing logic. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. there are four v ccql inputs. v ccqh (3) quiet external (high) power ?v ccqh is a quiet power source for i/o lines. this input must be tied externally to all other chip power inputs. the user must provide adequate decoup ling capacitors. there are three v ccqh inputs. v cca (3) address bus power ?v cca is an isolated power for sections of the address bus i/o drivers. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. there are three v cca inputs. v ccd (4) data bus power ?v ccd is an isolated power for sections of the data bus i/o drivers. this input must be tied externally to all other chip power inputs. th e user must provide adequate external decoupling capacitors. there are four v ccd inputs. v ccc (2) bus control power ?v ccc is an isolated power for the bus control i/o drivers. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. there are two v ccc inputs. v cch host power ?v cch is an isolated power for the hdi08 i/o drivers. this input must be tied externally to all other chip power inputs. the user must provide ade quate external decoupling capacitors. there is one v cch input. v ccs (2) shi, esai, esai_1, dax and timer power ?v ccs is an isolated power for the shi, esai, esai_1, dax and timer. this input must be tied externally to a ll other chip power inputs. the user must provide adequate external decoupling capacitors. there are two v ccs inputs. table 2-3 grounds ground name description gnd p pll ground ?gnd p is a ground dedicated for pll use. the connection should be provided with an extremely low-impedance path to ground. v ccp should be bypassed to gnd p by a 0.47 f capacitor located as close as possible to the chip package. there is one gnd p connection. gnd q (4) quiet ground ?gnd q is an isolated ground for the internal processing logic. this connection must be tied externally to all other chip ground connections . the user must provide adequate external decoupling capacitors. there are four gnd q connections. gnd a (4) address bus ground ?gnd a is an isolated ground for sections of the address bus i/o drivers. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. there are four gnd a connections.
DSP56366 technical data, rev. 3.1 2-4 freescale semiconductor 2.4 clock and pll 2.5 external memory expansion port (port a) when the DSP56366 enters a low-power standby mode (s top or wait), it releas es bus mastership and tri-states the relevant port a signals: a0?a17, d0?d23, aa0/ras0 ?aa2/ras2 , rd , wr , bb , cas . gnd d (4) data bus ground ?gnd d is an isolated ground for sections of the data bus i/o drivers. this connection must be tied externally to all other chip ground c onnections. the user must provide adequate external decoupling capacitors. there are four gnd d connections. gnd c (2) bus control ground ?gnd c is an isolated ground for the bus control i/o drivers. this connection must be tied externally to all other chip ground conn ections. the user must provide adequate external decoupling capacitors. there are two gnd c connections. gnd h host ground ?gnd h is an isolated ground for the hd08 i/o drivers. this connection must be tied externally to all other chip ground connections. th e user must provide adequate external decoupling capacitors. there is one gnd h connection. gnd s (2) shi, esai, esai_1, dax and timer ground ?gnd s is an isolated ground for the shi, esai, esai_1, dax and timer. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. there are two gnd s connections. table 2-4 clock and pll signals signal name type state during reset signal description extal input input external clock input ?an external clock source must be connected to extal in order to supply the clock to the internal clock generator and pll. this input cannot tolerate 5 v . pcap input input pll capacitor ?pcap is an input connecting an off-chip capacitor to the pll filter. connect one capacitor terminal to pcap and the other terminal to v ccp . if the pll is not used, pcap may be tied to v cc , gnd, or left floating. pinit/nmi input input pll initial/nonmaskable interrupt ?during assertion of reset , the value of pinit/nmi is written into the pll enable (pen) bit of the pll control register, determining whether the pll is en abled or disabled. after reset de assertion and during normal instruction processing, the pinit/nmi schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt (nmi) request internally synchronized to internal system clock. this input cannot tolerate 5 v . table 2-3 grounds (continued) ground name description
DSP56366 technical data, rev. 3.1 freescale semiconductor 2-5 2.5.1 external address bus 2.5.2 external data bus 2.5.3 external bus control table 2-5 external address bus signals signal name type state during reset signal description a0?a17 output tri-stated address bus ?when the dsp is the bus master, a0?a17 are active-high outputs that specify the address for external program and data memory accesses. otherwise, the signals are tri-stated. to minimize power dissipation, a0?a17 do not change state when external memory spaces are not being accessed. table 2-6 external data bus signals signal name type state during reset signal description d0?d23 input/out put tri-stated data bus ?when the dsp is the bus master, d0?d23 are active-high, bidirectional input/outputs that provide the bidirectio nal data bus for external program and data memory accesses. otherwise, d0?d23 are tri-stated. table 2-7 external bus control signals signal name type state during reset signal description aa0?aa2/ ras0 ?ras2 output tri-stated address attribute or row address strobe ?when defined as aa, these signals can be used as chip selects or additional address lines. when defined as ras , these signals can be used as ras for dram interface. these signals are tri-statable outputs with programmable polarity. cas output tri-stated column address strobe ? when the dsp is the bus master, cas is an active-low output used by dram to strobe the column address. otherwise, if the bus mastership enable (bme) bit in the dram control register is cleared, the signal is tri-stated. rd output tri-stated read enable ?when the dsp is the bus master, rd is an active-low output that is asserted to read external memory on the data bus (d0-d23). otherwise, rd is tri-stated. wr output tri-stated write enable ?when the dsp is the bus master, wr is an active-low output that is asserted to write external memory on the data bus (d0-d23). otherwise, wr is tri-stated.
DSP56366 technical data, rev. 3.1 2-6 freescale semiconductor ta input ignored input transfer acknowledge ?if the dsp is the bus master and there is no external bus activity, or the dsp is not the bus master, the ta input is ignored. the ta input is a data transfer acknowledge (dtack) function that can extend an external bus cycle indefinitely. any number of wait states (1, 2. . .infinity) may be added to the wait states inserted by the bcr by keeping ta deasserted. in typical operation, ta is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. the current bus cycle completes one clock period after ta is asserted synchronous to the internal system cloc k. the number of wait states is determined by the ta input or by the bus control register (bcr), whichever is longer. the bcr can be used to set the minimum number of wait states in external bus cycles. in order to use the ta functionality, the bcr must be programmed to at least one wait state. a zero wait state access cannot be extended by ta deassertion, otherwise improper operation may result. ta can operate synchronously or asynchronously, depending on the setting of the tas bit in the operating mode register (omr). ta functionality may not be used while performing dram type accesses, otherwise improper operation may result. br output output (deasserted) bus request ?br is an active-low output, never tri-stated. br is asserted when the dsp requests bus mastership. br is deasserted when the dsp no longer needs the bus. br may be asserted or deasserted independent of whether the DSP56366 is a bus master or a bus slave. bus ?parking? allows br to be deasserted even though the DSP56366 is the bus master. (see the description of bus ?parking? in the bb signal description.) the bus request hold (brh) bit in the bcr allows br to be asserted under software control even though the dsp does not need the bus. br is typically sent to an external bus arbitrator that controls the priority, pa rking, and tenure of each master on the same external bus. br is only affected by dsp requests for the external bus, never for the internal bus. during hardware reset, br is deasserted and the arbitration is reset to the bus slave state. table 2-7 external bus control signals (continued) signal name type state during reset signal description
DSP56366 technical data, rev. 3.1 freescale semiconductor 2-7 bg input ignored input bus grant ?bg is an active-low input. bg is asserted by an external bus arbitration circuit when the DSP56366 becomes the next bus master. when bg is asserted, the DSP56366 must wait until bb is deasserted before taking bus mastership. when bg is deasserted, bus mastership is typically given up at the end of the current bus cycle. this may o ccur in the middle of an instruction that requires more than one exte rnal bus cycle for execution. for proper bg operation, the asynchronous bus arbitration enable bit (abe) in the omr register must be set. bb input/output input bus busy ?bb is a bidirectional active-low input/output. bb indicates that the bus is active. only after bb is deasserted can the pending bus master become the bus master (and then assert the signal again). the bus master may keep bb asserted after ceasing bus activity regardless of whether br is asserted or deasserted. this is called ?bus parking? and allows the current bus master to reuse the bus without rearbitration until another device requires the bus. the deassertion of bb is done by an ?active pull-up? method (i.e., bb is driven high and then released and held high by an external pull-up resistor). for proper bb operation, the asynchronous bus arbitration enable bit (abe) in the omr register must be set. bb requires an external pull-up resistor. table 2-7 external bus control signals (continued) signal name type state during reset signal description
DSP56366 technical data, rev. 3.1 2-8 freescale semiconductor 2.6 interrupt and mode control the interrupt and mode control signals select the chip?s operating m ode as it comes out of hardware reset. after reset is deasserted, these inputs are hardware interrupt request lines. table 2-8 interrupt and mode control signal name type state during reset signal description moda/irqa input input mode select a/external interrupt request a? moda/irqa is an active-low schmitt-trigger input, internally sync hronized to the dsp clock. moda/irqa selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into the omr when the reset signal is deasserted. if the processor is in the stop standby state and the moda/irqa pin is pulled to gnd, the processor will exit the stop state. this input is 5 v tolerant . modb/irqb input input mode select b/external interrupt request b? modb/irqb is an active-low schmitt-trigger input, internally synchronized to the dsp clock. modb/irqb selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into omr when the reset signal is deasserted. this input is 5 v tolerant. modc/irqc input input mode select c/external interrupt request c? modc/irqc is an active-low schmitt-trigger input, internally sync hronized to the dsp clock. modc/irqc selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into omr when the reset signal is deasserted. this input is 5 v tolerant. modd/irqd input input mode select d/external interrupt request d ?modd/irqd is an active-low schmitt-trigger input, internally sync hronized to the dsp clock. modd/irqd selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into omr when the reset signal is deasserted. this input is 5 v tolerant. reset input input reset? reset is an active-low, schmitt-trigger inpu t. when asserted, the chip is placed in the reset state and the internal phase gen erator is reset. the schmitt-trigger input allows a slowly rising input (such as a capacit or charging) to reset the chip reliably. when the reset signal is deasserted, the initial chip operating mode is latched from the moda, modb, modc, and modd inputs. the reset signal must be asserted during power up. a stable extal signal must be supplied while reset is being asserted. this input is 5 v tolerant .
DSP56366 technical data, rev. 3.1 freescale semiconductor 2-9 2.7 parallel host interface (hdi08) the hdi08 provides a fast, 8-bit, para llel data port that may be connect ed directly to the host bus. the hdi08 supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers, microprocesso rs, dsps, and dma hardware. table 2-9 host interface signal name type state during reset signal description h0?h7 input/ output gpio disconnected host data? when hdi08 is programmed to interface a nonmultiplexed host bus and the hi function is selected, these signals are lines 0?7 of the bidirectional, tri-state data bus. had0?had7 input/ output gpio disconnected host address/data? when hdi08 is programmed to interface a multiplexed host bus and the hi function is selected, these signals are lines 0?7 of the address/data bidirectional, multiplexed, tri-state bus. pb0?pb7 input, output, or disconnected gpio disconnected port b 0?7 ?when the hdi08 is configured as gpio, these signals are individually programmable as input, output, or internally disconnected. the default state after reset for t hese signals is gpio disconnected. these inputs are 5 v tolerant. ha0 input gpio disconnected host address input 0 ?when the hdi08 is programmed to interface a nonmultiplexed host bus and the hi function is selected, this signal is line 0 of the host address input bus. has/ has input gpio disconnected host address strobe? when hdi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is the host address strobe (has) schmitt-trigger input. the polarity of the address strobe is programmable, but is configured active-low (has ) following reset. pb8 input, output, or disconnected gpio disconnected port b 8 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. ha1 input gpio disconnected host address input 1 ?when the hdi08 is programmed to interface a nonmultiplexed host bus and the hi function is selected, this signal is line 1 of the host address (ha1) input bus. ha8 input gpio disconnected host address 8 ?when hdi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is line 8 of the host address (ha8) input bus. pb9 input, output, or disconnected gpio disconnected port b 9 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant.
DSP56366 technical data, rev. 3.1 2-10 freescale semiconductor ha2 input gpio disconnected host address input 2 ?when the hdi08 is programmed to interface a non-multiplexed host bus and the hi func tion is selected, this signal is line 2 of the host address (ha2) input bus. ha9 input gpio disconnected host address 9 ?when hdi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is line 9 of the host address (ha9) input bus. pb10 input, output, or disconnected gpio disconnected port b 10 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. hrw input gpio disconnected host read/write ?when hdi08 is programmed to interface a single-data-strobe host bus and the hi func tion is selected, this signal is the host read/write (hrw) input. hrd / hrd input gpio disconnected host read data ?when hdi08 is programmed to interface a double-data-strobe host bus and the hi function is selected, this signal is the host read data strobe (hrd) schmitt-tr igger input. the polarity of the data strobe is programmable, but is configured as active-low (hrd ) after reset. pb11 input, output, or disconnected gpio disconnected port b 11 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. hds / hds input gpio disconnected host data strobe? when hdi08 is programmed to interface a single-data-strobe host bus and the hi func tion is selected, this signal is the host data strobe (hds) schmitt-trigge r input. the polarity of the data strobe is programmable, but is configured as active-low (hds ) following reset. hwr / hwr input gpio disconnected host write data ?when hdi08 is programmed to interface a double-data-strobe host bus and the hi function is selected, this signal is the host write data strobe (hwr) schmitt-trig ger input. the polarity of the data strobe is programmable, but is configured as active-low (hwr ) following reset. pb12 input, output, or disconnected gpio disconnected port b 12 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. hcs input gpio disconnected host chip select? when hdi08 is programmed to interface a nonmultiplexed host bus and the hi function is selected, this signal is the host chip select (hcs) input. the polarity of the chip select is programmable, but is configured active-low (hcs ) after reset. table 2-9 host interface (continued) signal name type state during reset signal description
DSP56366 technical data, rev. 3.1 freescale semiconductor 2-11 ha10 input gpio disconnected host address 10 ?when hdi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is line 10 of the host address (ha10) input bus. pb13 input, output, or disconnected gpio disconnected port b 13 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. horeq / horeq output gpio disconnected host request ?when hdi08 is programmed to interface a single host request host bus and the hi function is selected, this signal is the host request (horeq) output. the polarity of the host request is programmable, but is configured as active-low (horeq ) following reset. the host request may be programmed as a driven or open-drain output. htrq / htrq output gpio disconnected transmit host request? when hdi08 is programmed to interface a double host request host bus and the hi function is selected, this signal is the transmit host request (htrq) outpu t. the polarity of the host request is programmable, but is configured as active-low (htrq ) following reset. the host request may be programmed as a driven or open-drain output. pb14 input, output, or disconnected gpio disconnected port b 14 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. hack / hack input gpio disconnected host acknowledge ?when hdi08 is programmed to interface a single host request host bus and the hi function is selected, this signal is the host acknowledge (hack) schmitt-trigger input. the polarity of the host acknowledge is programmable, but is configured as active-low (hack ) after reset. hrrq / hrrq output gpio disconnected receive host request ?when hdi08 is programmed to interface a double host request host bus and the hi functi on is selected, this signal is the receive host request (hrrq) output. the polarity of the host request is programmable, but is configured as active-low (hrrq ) after reset. the host request may be programmed as a driven or open-drain output. pb15 input, output, or disconnected gpio disconnected port b 15 ?when the hdi08 is configured as gpio, this signal is individually programmed as input, output, or internally disconnected. the default state after reset for this signal is gpio disconnected. this input is 5 v tolerant. table 2-9 host interface (continued) signal name type state during reset signal description
DSP56366 technical data, rev. 3.1 2-12 freescale semiconductor 2.8 serial host interface the shi has five i/o signals that can be configured to allow the sh i to operate in either spi or i 2 c mode. table 2-10 serial host interface signals signal name signal type state during reset signal description sck input or output tri-stated spi serial clock ?the sck signal is an output when the spi is configured as a master and a schmitt-trigger input when the spi is configured as a slave. when the spi is configured as a master, the sck signal is derived from the internal shi clock generator. when the spi is configured as a slave, the sck signal is an input, and the clock signal from the external master synchronizes the data transfer. the sck signal is ignored by the spi if it is defined as a slave and the slave select (ss ) signal is not asserted. in both the master and slave spi devices, data is shifted on one edge of the sck signal and is sampled on the opposite edge where data is stable. edge polarity is determined by the spi transfer protocol. scl input or output tri-stated i 2 c serial clock ?scl carries the clock for i 2 c bus transactions in the i 2 c mode. scl is a schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. scl should be connected to v cc through a pull-up resistor. this signal is tri-stated during hardware, software, and individual reset. thus, there is no need for an external pull-up in this state. this input is 5 v tolerant. miso input or output tri-stated spi master-in-slave-out ?when the spi is configured as a master, miso is the master data input line. the miso signal is used in conjunction with the mosi signal for transmitting and receiving serial data. this signal is a schmitt-trigger input when configured for the spi master mode, an output when configured for the spi slave mode, and tri-stated if configur ed for the spi slave mode when ss is deasserted. an external pull-up resistor is not required for spi operation. sda input or open-drain output tri-stated i 2 c data and acknowledge ?in i 2 c mode, sda is a schmitt-trigger input when receiving and an open-drain output when transmitting. sda should be connected to v cc through a pull-up resistor. sda carries the data for i 2 c transactions. the data in sda must be stable during the high period of scl. the data in sda is only allowed to change when scl is low. when the bus is free, sda is high. the sda line is only allowed to change during the time scl is high in the case of start and stop events. a high-to-low transition of the sda line while scl is high is a unique situation, and is defined as the start ev ent. a low-to-high transition of sda while scl is high is a unique situation defined as the stop event. this signal is tri-stated during hardware, software, and individual reset. thus, there is no need for an external pull-up in this state. this input is 5 v tolerant. mosi input or output tri-stated spi master-out-slave-in ?when the spi is configured as a master, mosi is the master data output line. the mosi sign al is used in conjunction with the miso signal for transmitting and receiving serial data. mosi is the slave data input line when the spi is configured as a slave. this signal is a schmitt-trigger input when configured for the spi slave mode.
DSP56366 technical data, rev. 3.1 freescale semiconductor 2-13 ha0 input i 2 c slave address 0 ?this signal uses a schmitt-trigger input when configured for the i 2 c mode. when configured for i 2 c slave mode, the ha0 signal is used to form the slave device address. ha0 is ignored when configured for the i 2 c master mode. this signal is tri-stated during hardware, software, and individual reset. thus, there is no need for an external pull-up in this state. this input is 5 v tolerant. ss input tri-stated spi slave select ?this signal is an active low schmitt-trigger input when configured for the spi mode. when configured for the spi slave mode, this signal is used to enable the spi slave for trans fer. when configured for the spi master mode, this signal should be kept deasserted (pulled high). if it is asserted while configured as spi master, a bus error condition is flagged. if ss is deasserted, the shi ignores sck clocks and keeps the miso output signal in the high-impedance state. ha2 input i 2 c slave address 2 ?this signal uses a schmitt-trigger input when configured for the i 2 c mode. when configured for the i 2 c slave mode, the ha2 signal is used to form the slave device address. ha2 is ignored in the i 2 c master mode. this signal is tri-stated during hardware, software, and individual reset. thus, there is no need for an external pull-up in this state. this input is 5 v tolerant . hreq input or output tri-stated host request ?this signal is an active low schmitt-trigger input when configured for the master mode but an active low output when configured for the slave mode. when configured for the slave mode, hreq is asserted to indicate that the shi is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. when configured for the master mode, hreq is an input. when asserted by the external slave device, it will trigger the start of the data word transfer by the master. after finishing th e data word transfer, the master will await the next assertion of hreq to proceed to the next transfer. this signal is tri-stated during hardware, software, personal reset, or when the hreq1?hreq0 bits in the hcsr are cleared. there is no need for external pull-up in this state. this input is 5 v tole rant. table 2-10 serial host interface signals (continued) signal name signal type state during reset signal description
DSP56366 technical data, rev. 3.1 2-14 freescale semiconductor 2.9 enhanced serial audio interface table 2-11 enhanced serial audio interface signals signal name signal type state during reset signal description hckr input or output gpio disconnected high frequency clock for receiver ?when programmed as an input, this signal provides a high frequency clock source for the esai receiver as an alternate to the dsp core clock. when programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [dacs]) or as an additional system clock. pc2 input, output, or disconnected gpio disconnected port c 2 ?when the esai is configured as gp io, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant. hckt input or output gpio disconnected high frequency clock for transmitter ?when programmed as an input, this signal provides a high frequency clock source for the esai transmitter as an alternate to the dsp core clock. when programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external dacs) or as an additional system clock. pc5 input, output, or disconnected gpio disconnected port c 5 ?when the esai is configured as gp io, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant. fsr input or output gpio disconnected frame sync for receiver ?this is the receiver frame sync input/output signal. in the asynchronous mode (syn=0), the fsr pin operates as the frame sync input or output used by all the enabled receivers. in the synchronous mode (syn=1), it operates as either the serial flag 1 pin (tebe=0), or as the transmi tter external buffer enable control (tebe=1, rfsd=1). when this pin is configured as serial flag pin, its direction is determined by the rfsd bit in the rccr register. when conf igured as the output flag of1, this pin will reflect the value of the of1 bit in the saicr register, and the data in the of1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input flag if1, the data value at the pin will be stored in the if1 bit in the saisr register, synchronized by the frame sync in normal mode or the slot in network mode. pc1 input, output, or disconnected gpio disconnected port c 1 ?when the esai is configured as gp io, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant.
DSP56366 technical data, rev. 3.1 freescale semiconductor 2-15 fst input or output gpio disconnected frame sync for transmitter ?this is the transmitter frame sync input/output signal. for synchronous mode, this signal is the frame sync for both transmitters and receivers. for asynchronous mode, fst is the frame sync for the transmitters only. the direction is determined by the transmitter frame sync direction (tfsd) bit in the esai transmit clock control register (tccr). pc4 input, output, or disconnected port c 4 ?when the esai is configured as gp io, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant. sckr input or output gpio disconnected receiver serial clock ?sckr provides the receiver serial bit clock for the esai. the sckr operates as a clock in put or output used by all the enabled receivers in the asynchronous mode (syn=0), or as serial flag 0 pin in the synchronous mode (syn=1). when this pin is configured as serial flag pin, its direction is determined by the rckd bit in the rccr register. when confi gured as the output flag of0, this pin will reflect the value of the of0 bit in the saicr register, and the data in the of0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input flag if0, the data value at the pin will be stored in the if0 bit in the saisr register, synchronized by the frame sync in normal mode or the slot in network mode. pc0 input, output, or disconnected gpio disconnected port c 0 ?when the esai is configured as gp io, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant. sckt input or output gpio disconnected transmitter serial clock ?this signal provides the serial bit rate clock for the esai. sckt is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. pc3 input, output, or disconnected gpio disconnected port c 3 ?when the esai is configured as gp io, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant. sdo5 output gpio disconnected serial data output 5 ?when programmed as a transmitter, sdo5 is used to transmit data from the tx5 seri al transmit shift register. sdi0 input gpio disconnected serial data input 0 ?when programmed as a receiver, sdi0 is used to receive serial data into the rx0 serial receive shift register. table 2-11 enhanced serial audio interface signals (continued) signal name signal type state during reset signal description
DSP56366 technical data, rev. 3.1 2-16 freescale semiconductor pc6 input, output, or disconnected gpio disconnected port c 6 ?when the esai is configured as gp io, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant. sdo4 output gpio disconnected serial data output 4 ?when programmed as a transmitter, sdo4 is used to transmit data from the tx4 seri al transmit shift register. sdi1 input gpio disconnected serial data input 1 ?when programmed as a receiver, sdi1 is used to receive serial data into the rx1 serial receive shift register. pc7 input, output, or disconnected gpio disconnected port c 7 ?when the esai is configured as gp io, this signal is individually programmable as input, output, or internally disconnected. the default state after re set is gpio disconnected. this input is 5 v tolerant. sdo3/sd o3_1 output gpio disconnected serial data output 3 ?when programmed as a transmitter, sdo3 is used to transmit data from the tx3 seri al transmit shift register. when enabled for esai_1 operation, this is the esai_1 serial data output 3. sdi2/ sdi2_1 input gpio disconnected serial data input 2 ?when programmed as a receiver, sdi2 is used to receive serial data into the rx2 serial receive shift register. when enabled for esai_1 operat ion, this is the esai_ 1 serial data input 2. pc8/pe8 input, output, or disconnected gpio disconnected port c 8 ?when the esai is configured as gp io, this signal is individually programmable as input, output, or internally disconnected. when enabled for esai_1 gpio, this is the port e 8 signal. the default state after re set is gpio disconnected. this input is 5 v tolerant. sdo2/ sdo2_1 output gpio disconnected serial data output 2 ?when programmed as a transmitter, sdo2 is used to transmit data from the tx2 seri al transmit shift register. when enabled for esai_1 operation, this is the esai_1 serial data output 2. sdi3/sdi3 _1 input gpio disconnected serial data input 3 ?when programmed as a receiver, sdi3 is used to receive serial data into the rx3 serial receive shift register. when enabled for esai_1 operat ion, this is the esai_ 1 serial data input 3. pc9/pe9 input, output, or disconnected gpio disconnected port c 9 ?when the esai is configured as gp io, this signal is individually programmable as input, output, or internally disconnected. when enabled for esai_1 gpio, this is the port e 9 signal. the default state after re set is gpio disconnected. this input is 5 v tolerant. table 2-11 enhanced serial audio interface signals (continued) signal name signal type state during reset signal description
DSP56366 technical data, rev. 3.1 freescale semiconductor 2-17 sdo1/ sdo1_1 output gpio disconnected serial data output 1 ?sdo1 is used to transmit data from the tx1 serial transmit shift register. when enabled for esai_1 operation, this is the esai_1 serial data output 1. pc10/ pe10 input, output, or disconnected gpio disconnected port c 10 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. when enabled for esai_1 gpio, this is the port e 10 signal. the default state after re set is gpio disconnected. this input is 5 v tolerant. sdo0/sd o0_1 output gpio disconnected serial data output 0 ?sdo0 is used to transmit data from the tx0 serial transmit shift register. when enabled for esai_1 operation, this is the esai_1 serial data output 0. pc11/ pe11 input, output, or disconnected gpio disconnected port c 11 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. when enabled for esai_1 gpio, this is the port e 11 signal. the default state after re set is gpio disconnected. this input is 5 v tolerant. table 2-11 enhanced serial audio interface signals (continued) signal name signal type state during reset signal description
DSP56366 technical data, rev. 3.1 2-18 freescale semiconductor 2.10 enhanced serial audio interface_1 table 2-12 enhanced serial audio interface_1 signals signal name signal type state during reset signal description fsr_1 input or output gpio disconnected frame sync for receiver_1 ?this is the receiver frame sync input/output signal. in the asynchronous mode (syn=0), the fsr pin operates as the frame sync input or output used by all the enabled receivers. in the synchronous mode (syn=1), it operates as either the serial flag 1 pin (tebe=0), or as the transmi tter external buffer enable control (tebe=1, rfsd=1). when this pin is configured as serial fl ag pin, its direction is determined by the rfsd bit in the rccr register. when configured as t he output flag of1, this pin will reflect the value of the of1 bit in the saicr register, and the data in the of1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input flag if1, the data value at the pin will be stored in the if1 bit in the saisr register, synchronized by the frame sync in normal mode or the slot in network mode. pe1 input, output, or disconnected gpio disconnected port e 1 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input cannot tolerate 5 v. fst_1 input or output gpio disconnected frame sync for transmitter_1 ?this is the transmitter frame sync input/output signal. for synchronous mode, this signal is the frame sync for both transmitters and receivers. for asynchronous mode, fst is the frame sync for the transmitters only. the direction is determined by the transmitter frame sync direction (tfsd) bit in th e esai transmit clock control register (tccr). pe4 input, output, or disconnected gpio disconnected port e 4 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input cannot tolerate 5 v. sckr_1 input or output gpio disconnected receiver serial clock_1 ?sckr provides the receiver serial bit clock for the esai. the sckr operates as a cloc k input or output used by all the enabled receivers in the asynchronous mode (syn=0), or as serial flag 0 pin in the synchronous mode (syn=1). when this pin is configured as serial fl ag pin, its direction is determined by the rckd bit in the rccr register. when configured as the output flag of0, this pin will reflect the value of the of0 bit in the saicr register, and the data in the of0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input flag if0, the data value at the pin will be stored in the if0 bit in the saisr register, synchronized by the frame sync in normal mode or the slot in network mode.
DSP56366 technical data, rev. 3.1 freescale semiconductor 2-19 pe0 input, output, or disconnected gpio disconnected port e 0 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input cannot tolerate 5 v. sckt_1 input or output gpio disconnected transmitter serial clock_1 ?this signal provides the serial bit rate clock for the esai. sckt is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. pe3 input, output, or disconnected gpio disconnected port e 3 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input cannot tolerate 5 v. sdo5_1 output gpio disconnected serial data output 5_1 ?when programmed as a transmitter, sdo5 is used to transmit data from the tx5 serial transmit shift register. sdi0_1 input gpio disconnected serial data input 0_1 ?when programmed as a receiver, sdi0 is used to receive serial data into the rx0 serial receive shift register. pe6 input, output, or disconnected gpio disconnected port e 6 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input cannot tolerate 5 v. sdo4_1 output gpio disconnected serial data output 4_1 ?when programmed as a transmitter, sdo4 is used to transmit data from the tx4 serial transmit shift register. sdi1_1 input gpio disconnected serial data input 1_1 ?when programmed as a receiver, sdi1 is used to receive serial data into the rx1 serial receive shift register. pe7 input, output, or disconnected gpio disconnected port e 7 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input is 5 v tolerant. table 2-12 enhanced serial audio interface_1 signals signal name signal type state during reset signal description
DSP56366 technical data, rev. 3.1 2-20 freescale semiconductor 2.11 spdif transmitter digital audio interface 2.12 timer table 2-13 digital audio interface (dax) signals signal name type state during reset signal description aci input gpio disconnected audio clock input ?this is the dax clock input. when programmed to use an external clock, this input supplies the dax clock. the external clock frequency must be 256, 384, or 512 times the audio sampling frequency (256 fs, 384 fs or 512 fs, respectively). pd0 input, output, or disconnected gpio disconnected port d 0 ?when the dax is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input is 5 v tolerant. ado output gpio disconnected digital audio data output ?this signal is an audio and non-audio output in the form of aes/ebu, cp340 and ie c958 data in a biphase mark format. pd1 input, output, or disconnected gpio disconnected port d 1 ?when the dax is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after rese t is gpio disconnected. this input is 5 v tolerant. table 2-14 timer signal signal name type state during reset signal description tio0 input or output input timer 0 schmitt-trigger input/output ?when timer 0 functions as an external event counter or in measur ement mode, tio0 is used as input. when timer 0 functions in watchdog, timer, or pulse modulation mode, tio0 is used as output. the default mode after reset is gpio input. this can be changed to output or configured as a timer input/output throug h the timer 0 control/status register (tcsr0). if tio0 is not being used, it is recommended to either define it as gpio output immediately at the beginning of operation or leave it defined as gpio input but connected to vcc through a pull-up resistor in order to ensure a stable logic level at this input. this input is 5 v tolerant.
DSP56366 technical data, rev. 3.1 freescale semiconductor 2-21 2.13 jtag/once interface table 2-15 jtag/once interface signal name signal type state during reset signal description tck input input test clock ?tck is a test clock input signal used to synchronize the jtag test logic. it has an internal pull-up resistor. this input is 5 v tolerant. tdi input input test data input ?tdi is a test data serial input sign al used for test instructions and data. tdi is sampled on the rising edge of tc k and has an internal pull-up resistor. this input is 5 v tolerant. tdo output tri-stated test data output ?tdo is a test data serial output signal used for test instructions and data. tdo is tri-statable and is acti vely driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tck. tms input input test mode select ?tms is an input signal used to sequence the test controller?s state machine. tms is sampled on the rising edge of tck and has an internal pull-up resistor. this input is 5 v tolerant.
DSP56366 technical data, rev. 3.1 2-22 freescale semiconductor notes
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-1 3 specifications 3.1 introduction the DSP56366 is a high density cmos device with transistor-trans istor logic (ttl) compatible inputs and outputs. the DSP56366 specificati ons are preliminary and are from design simulations, and may not be fully tested or guaranteed. fina lized specifications will be publishe d after full characterization and device qualifications are complete. 3.2 maximum ratings caution this device contains circuitry protecti ng against damage due to high static voltage or electrical fields. however, normal preca utions should be taken to avoid exceeding maximum voltage ra tings. reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (e.g., either gnd or v cc ). the suggested value for a pullup or pulldown resistor is 10 k . note in the calculation of timing requireme nts, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. a maximum specification is calculat ed using a worst case variation of process parameter valu es in one direction. the minimum specification is calculated using the wo rst case for the same parameters in the opposite direction. therefore, a ?m aximum? value for a specification will never occur in the sa me device that has a ?m inimum? value for another specification; adding a maximum to a minimum represents a condition that can never exist. table 3-1 maximum ratings rating 1 symbol value 1, 2 unit supply voltage v cc ? 0.3 to +4.0 v all input voltages excluding ?5 v tolerant? inputs 3 v in gnd -0.3 to v cc + 0.3 v all ?5 v tolerant? input voltages 3 v in5 gnd ? 0.3 to v cc + 3.95 v current drain per pin excluding v cc and gnd i 10 ma
DSP56366 technical data, rev. 3.1 3-2 freescale semiconductor 3.3 thermal characteristics operating temperature range t j ? 40 to +110 c storage temperature t stg ? 55 to +125 c 1 gnd = 0 v, v cc = 3.3 v 0.16 v, t j = ?40 c to +110 c, c l = 50 pf 2 absolute maximum ratings are stress ratings only, and functiona l operation at the maximum is not guaranteed. stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 3 caution: all ?5 v tolerant? input voltages must not be more than 3. 95 v greater than the supply voltage; this restriction applies to ?power on?, as well as during normal operation. in an y case, the input voltages cannot be more than 5.75 v. ?5 v tolerant? inputs are inputs that tolerate 5 v. table 3-2 thermal characteristics characteristic symbo l lqfp value unit junction-to-ambient thermal resistance 1, 2 natural convection 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other componen ts on the board, and board thermal resistance. 2 per semi g38-87 and jedec jesd51-2 with the single layer board horizontal. r ja or ja 37 c/w junction-to-case thermal resistance 3 3 thermal resistance between the die and the case top surf ace as measured by the cold plate method (mil spec-883 method 1012.1). r jc or jc 7 c/w thermal characterization parameter 4 natural convection 4 thermal characterization parameter indicating the tem perature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. jt 2.0 c/w table 3-1 maximum ratings (continued) rating 1 symbol value 1, 2 unit
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-3 3.4 dc electrical characteristics table 3-3 dc electrical characteristics 1 1 v cc = 3.3 v .16 v; t j = ? 40c to +110c, c l = 50 pf characteristics symbol min typ max unit supply voltage v cc 3.14 3.3 3.46 v input high voltage ? d(0:23), bg , bb , ta , esai_1 (except sdo4_1) ?mod 2 /irq 2 , reset , pinit/nmi and all jtag/esai/timer/hdi08/dax/esai_1 (only sdo4_1) /shi (spi mode) ?shi (i2c mode) ? extal 3 2 refers to moda/irqa , modb/irqb , modc/irqc ,and modd/irqd pins. 3 driving extal to the low v ihx or the high v ilx value may cause additional power consumption (dc current). to minimize power consumption, the minimum v ihx should be no lower than 0.9 v cc and the maximum v ilx should be no higher than 0.1 v cc . v ih v ihp v ihp v ihx 2.0 2.0 1.5 0.8 v cc ? ? ? ? v cc + 3.95 v cc + 3.95 v cc v input low voltage ? d(0:23), bg , bb , ta , esai_1 (except sdo4_1) ?mod 2 /irq 2 , reset , pinit/nmi and all jtag/esai/timer/hdi08/dax/esai_1 (only sdo4_1) /shi (spi mode) ?shi (i2c mode) ? extal 3 v il v ilp v ilp v ilx ?0.3 ?0.3 ?0.3 ?0.3 ? ? ? ? 0.8 0.8 0.3 x v cc 0.2 x v cc v input leakage current i in ?10 ? 10 a high impedance (off-state) input current (@ 2.4 v / 0.4 v) i tsi ?10 ? 10 a output high voltage ?ttl (i oh = ?0.4 ma) 4,5 ? cmos (i oh = ?10 a) 4 4 periodically sampled and not 100% tested. 5 this characteristic does not apply to pcap. v oh v oh 2.4 v cc ? 0.01 ? ? ? ? v output low voltage ?ttl (i ol = 3.0 ma, open-drain pins i ol = 6.7 ma) 4,5 ? cmos (i ol = 10 a) 4 v ol v ol ? ? ? ? 0.4 0.01 v internal supply current 6 at internal clock of 120mhz ? in normal mode ? in wait mode ? in stop mode 7 i cci i ccw i ccs ? ? ? 116 7.3 1 200 25 10 ma pll supply current ? 1 2.5 ma input capacitance 4 c in ? ? 10 pf
DSP56366 technical data, rev. 3.1 3-4 freescale semiconductor 3.5 ac electrical characteristics the timing waveforms shown in th e ac electrical characteristics section are tested with a v il maximum of 0.3 v and a v ih minimum of 2.4 v for all pins except extal, which is tested using the input levels shown in note 3 of the previous ta ble. ac timing specificat ions, which are referenced to a device input signal, are measured in production wi th respect to the 50% point of the respective input signal?s transition. DSP56366 output levels are measured with the production test machine v ol and v oh reference levels set at 0.4 v and 2.4 v, respectively. note although the minimum value for the frequency of extal is 0 mhz, the device ac test conditions are 15 mhz and rated speed. 3.6 internal clocks 6 appendix a, "power c onsumption benchmark" provides a formula to compute th e estimated current requirements in normal mode. in order to obtain these re sults, all inputs must be terminated (i.e., not allowed to float). measurements are based on synthetic intensive dsp benchm arks. the power consumption numbers in this specification are 90% of the measured results of this benchmark. this reflects typical dsp applications. typical internal supply current is measured with v cc = 3.3 v at t j = 110c. maximum internal s upply current is measured with v cc = 3.46 v at t j = 110c. 7 in order to obtain these results, all inputs, which are not di sconnected at stop mode, must be terminated (i.e., not allowed to float). table 3-4 internal clocks characteristics symbol expression 1, 2 min typ max internal operation frequency with pll enabled f?(ef mf)/(pdf df) ? internal operation frequency with pll disabled f? ef/2 ? internal clock high period ? with pll disabled ? with pll enabled and mf 4 ? with pll enabled and mf > 4 t h ? 0.49 et c pdf df/mf 0.47 et c pdf df/mf et c ? ? ? 0.51 et c pdf df/mf 0.53 et c pdf df/mf internal clock low period ? with pll disabled ? with pll enabled and mf 4 ? with pll enabled and mf > 4 t l ? 0.49 et c pdf df/mf 0.47 et c pdf df/mf et c ? ? ? 0.51 et c pdf df/mf 0.53 et c pdf df/mf internal clock cycl e time wi th pll enabled t c ?et c pdf df/mf ?
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-5 3.7 external clock operation the DSP56366 system clock is an ex ternally supplied square wave vol tage source connected to extal (see figure 3-1 ). figure 3-1 external clock timing internal clock cycl e time wi th pll disabled t c ?2 et c ? instruction cycle time i cyc ?t c ? 1 df = division factor ef = external frequency et c = external clock cycle mf = multiplication factor pdf = predivision factor t c = internal clock cycle 2 see the pll and clock generation section in the dsp56300 family manual for a detailed discussion of the pll. table 3-5 clock operation no. characteristics symbol min max 1 frequency of extal (extal pin frequency) the rise and fall time of this ex ternal clock should be 3 ns maximum. ef 0 120.0 2 extal input high 1, 2 ? with pll disabled (46.7%?53.3% duty cycle 3 ) ? with pll enabled (42.5%?57.5% duty cycle 3 ) et h 3.89 ns 3.54 ns 157.0 s 3 extal input low 1, 2 ? with pll disabled (46.7%?53.3% duty cycle 3 ) ? with pll enabled (42.5%?57.5% duty cycle 3 ) et l 3.89 ns 3.54 ns 157.0 s table 3-4 internal clocks characteristics symbol expression 1, 2 min typ max extal v ilc v ihc midpoint notes the midpoint is 0.5 (v ihc + v ilc ). eth etl etc 3 4 2
DSP56366 technical data, rev. 3.1 3-6 freescale semiconductor 3.8 phase lock loop (pll) characteristics 3.9 reset, stop, mode select, and interrupt timing 4 extal cycle time 2 ? with pll disabled ? with pll enabled et c 8.33 ns 8.33 ns 273.1 s 7 instruction cycle time = i cyc = t c 4, 2 ? with pll disabled ? with pll enabled i cyc 16.66 ns 8.33 ns 8.53 s 1 measured at 50% of the input transition. 2 the maximum value for pll enabled is given for minimum v co and maximum mf. 3 the indicated duty cycle is for the specified maximum frequency for which a part is rated. the minimum clock high or low time required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specif ied duty cycle as long as the minimum high time and low time requirements are met. 4 the maximum value for pll enabled is given for minimum vco and maximum df. table 3-6 pll characteristics characteristics min max unit v co frequency when pll enabled (mf e f 2/pdf) 30 240 mhz pll external capacitor (pcap pin to v ccp ) (c pcap ) 1 ? @ mf 4 ? @ mf > 4 1 c pcap is the value of the pll capacitor (connected between the pcap pin and v ccp ). the recommended value in pf for c pcap can be computed from one of the following equations: (mf x 680)-120 , for mf 4 or mf x 1100 , for mf > 4. (mf 580) ? 100 mf 830 (mf 780) ? 140 mf 1470 pf table 3-7 reset, stop, mode select, and interrupt timing 1 no. characteristics expression min max unit 8 delay from reset assertion to all pins at reset value 2 ? ? 26.0 ns 9 required reset duration 3 ? power on, external clock generator, pll disabled ? power on, external clock generator, pll enabled ? during normal operation 50 et c 1000 et c 2.5 t c 416.7 8.3 20.8 ? ? ? ns s ns 10 delay from asynchronous reset deassertion to first external address output (internal reset deassertion) 4 ?minimum ? maximum 3.25 t c + 2.0 20.25 t c + 7.50 29.1 ? ? 176.2 ns ns 13 mode select setup time 30.0 ? ns table 3-5 clock operation (continued) no. characteristics symbol min max
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-7 14 mode select hold time 0.0 ? ns 15 minimum edge-triggered interrupt request assertion width 5.5 ? ns 16 minimum edge-triggered interrupt request deassertion width 5.5 ? ns 17 delay from irqa , irqb , irqc , irqd , nmi assertion to external memory access address out valid ? caused by first interrupt instruction fetch ? caused by first interrupt instruction execution 4.25 t c + 2.0 7.25 t c + 2.0 37.4 62.4 ? ? ns ns 18 delay from irqa , irqb , irqc , irqd , nmi assertion to general-purpose transfer output valid caused by first interrupt instruction execution 10 t c + 5.0 88.3 ? ns 19 delay from address output vali d caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts 5 3.75 t c + ws t c ? 10.94 ? note 6 ns 20 delay from rd assertion to interrupt request deassertion for level sensitive fast interrupts 5 3.25 t c + ws t c ? 10.94 ? note 6 ns 21 delay from wr assertion to interrupt request deassertion for level sensitive fast interrupts 5 ? dram for all ws ? sram ws = 1 ? sram ws = 2, 3 ? sram ws 4 (ws + 3.5) t c ? 10.94 (ws + 3.5) t c ? 10.94 (ws + 3) t c ? 10.94 (ws + 2.5) t c ? 10.94 ? ? ? ? note 6 note 6 note 6 note 6 ns 24 duration for irqa assertion to recover from stop state 4.9 ? 25 delay from irqa assertion to fetch of first instruction (when exiting stop) 2, 7 ? pll is not active during stop (pctl bit 17 = 0) and stop delay is enabled (omr bit 6 = 0) ? pll is not active during stop (pctl bit 17 = 0) and stop delay is not enabled (omr bit 6 = 1) ? pll is active during stop (pctl bit 17 = 1) (implies no stop delay) plc et c pdf + (128 k ? plc/2) t c plc et c pdf + (23.75 0.5) t c (8.25 0.5) t c ? ? 64.6 ? ? 72.9 ms ms ms 26 duration of level sensitive irqa assertion to ensure interrupt service (when exiting stop) 2, 7 ? pll is not active during stop (pctl bit 17 = 0) and stop delay is enabled (omr bit 6 = 0) ? pll is not active during stop (pctl bit 17 = 0) and stop delay is not enabled (omr bit 6 = 1) ? pll is active during stop (pctl bit 17 = 1) (implies no stop delay) plc et c pdf + (128k ? plc/2) t c plc et c pdf + (20.5 0.5) t c 5.5 t c ? ? 45.8 ? ? ? ms ms ns table 3-7 reset, stop, mode select, and interrupt timing 1 (continued) no. characteristics expression min max unit
DSP56366 technical data, rev. 3.1 3-8 freescale semiconductor 27 interrupt requests rate ? hdi08, esai, esai_1, shi, dax, timer ?dma ?irq , nmi (edge trigger) ?irq (level trigger) 12t c 8t c 8t c 12t c ? ? ? ? 100.0 66.7 66.7 100.0 ns ns ns ns 28 dma requests rate ? data read from hdi08, esai, esai_1, shi, dax ? data write to hdi08, esai, esai_1, shi, dax ?timer ?irq , nmi (edge trigger) 6t c 7t c 2t c 3t c ? ? ? 50.0 58.0 16.7 25.0 ns ns ns 29 delay from irqa , irqb , irqc , irqd , nmi assertion to external memory (dma source) access address out valid 4.25 t c + 2.0 37.4 ? ns 1 v cc = 3.3 v 0.16 v; t j = ?40c to + 110c, c l = 50 pf 2 periodically sampled and not 100% tested. 3 reset duration is measured during the time in which reset is asserted, v cc is valid, and the extal input is active and valid. when the v cc is valid, but the other ?required reset duration? conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. designs should minimize this state to the shortest possible duration. 4 if pll does not lose lock. 5 when using fast interrupts and irqa , irqb , irqc , and irqd are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. to avoid these timing restrictions, the deasserted edge-triggered mode is recommended when using fast interrupts. long interrupts are recommended when using level-sensitive mode. 6 ws = number of wait states (measured in clock cycles, number of t c ). use expression to compute maximum value. 7 this timing depends on several settings: for pll disable, using external clock (pctl bit 16 = 1), no stabilization delay is required and recovery time will be defined by the pctl bit 17 and omr bit 6 settings. for pll enable, if pctl bit 17 is 0, the pll is shutdown durin g stop. recovering from stop requires the pll to get locked. the pll lock procedure duration, pll lock cycles (plc), may be in the range of 0 to 1000 cycles. this procedure occurs in parallel with the stop delay counter, and stop recovery will e nd when the last of these two events occurs: the stop delay counter completes count or pll lock procedure completion. plc value for pll disable is 0. the maximum value for et c is 4096 (maximum mf) divided by the desired inter nal frequency (i.e., for 120 mhz it is 4096/120 mhz = 34.1 s). during the stabilization period, t c , t h , and t l will not be constant, and their width may vary, so timing may vary as well. table 3-7 reset, stop, mode select, and interrupt timing 1 (continued) no. characteristics expression min max unit
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-9 figure 3-2 reset timing figure 3-3 external fast interrupt timing v ih reset reset value first fetch all pins a0?a17 8 9 10 aa0460 a0?a17 rd a) first interrupt instruction execution general purpose i/o irqa , irqb , irqc , irqd , nmi b) general purpose i/o irqa , irqb , irqc , irqd , nmi wr 20 21 19 17 18 first interrupt instruction execution/fetch
DSP56366 technical data, rev. 3.1 3-10 freescale semiconductor figure 3-4 external interrupt ti ming (negative edge-triggered) figure 3-5 operating mode select timing figure 3-6 recovery from stop state using irqa irqa , irqb , irqc, irqd , nmi irqa , irqb , irqc, irqd , nmi 15 16 aa0463 reset moda, modb, modc, modd, pinit v ih irqa , irqb , irqd , nmi v ih v il v ih v il 13 14 aa0465 first instruction fetch irqa a0?a17 24 25 aa0466
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-11 figure 3-7 recovery from stop state using irqa interrupt service figure 3-8 external memory access (dma source) timing 3.10 external memory expansion port (port a) 3.10.1 sram timing table 3-8 sram read and write accesses 1 no. characteristics symbol expression 2 min max unit 100 address valid and aa assertion pulse width t rc , t wc (ws + 1) t c ? 4.0 [1 ws 3] 12.0 ? ns (ws + 2) t c ? 4.0 [4 ws 7] 46.0 ? ns (ws + 3) t c ? 4.0 [ws 8] 87.0 ? ns irqa a0?a17 first irqa interrupt instruction fetch 26 25 aa0467 29 dma source address first interrupt instruction execution a0?a17 rd wr irqa , irqb , irqc, irqd , nmi aa1104
DSP56366 technical data, rev. 3.1 3-12 freescale semiconductor 101 address and aa valid to wr assertion t as 0.25 t c ? 2.0 [ws = 1] 0.1 ? ns 1.25 t c ? 2.0 [ws 4] 8.4 ? ns 102 wr assertion pulse width t wp 1.5 t c ? 4.0 [ws = 1] 8.5 ? ns all frequencies: ws t c ? 4.0 [2 ws 3] 12.7 ? ns (ws ? 0.5) t c ? 4.0 [ws 4] 25.2 ? ns 103 wr deassertion to address not valid t wr 0.25 t c ? 2.0 [1 ws 3] 0.1 ? ns 1.25 t c ? 2.0 [4 ws 7] 8.4 ? ns 2.25 t c ? 2.0 [ws 8] 16.7 ? ns all frequencies: 1.25 t c ? 4.0 [4 ws 7] 6.4 ? ns 2.25 t c ? 4.0 [ws 8] 14.7 ? ns 104 address and aa valid to input data valid t aa , t ac (ws + 0.75) t c ? 7.0 [ws 1] ?7.6ns 105 rd assertion to input data valid t oe (ws + 0.25) t c ? 7.0 [ws 1] ?3.4ns 106 rd deassertion to data not valid (data hold time) t ohz 0.0 ? ns 107 address valid to wr deassertion 3 t aw (ws + 0.75) t c ? 4.0 [ws 1] 10.6 ? ns 108 data valid to wr deassertion (data setup time) t ds (t dw )(ws ? 0.25) t c ? 3.0 [ws 1] 3.2 ? ns table 3-8 sram read and write accesses 1 (continued) no. characteristics symbol expression 2 min max unit
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-13 109 data hold time from wr deassertion t dh 0.25 t c ? 2.0 [1 ws 3] 0.1 ? ns 1.25 t c ? 2.0 [4 ws 7] 8.4 ? ns 2.25 t c ? 2.0 [ws 8] 16.7 ? ns 110 wr assertion to data active ? 0.75 t c ? 3.7 [ws = 1] 2.5 ? ns 0.25 t c ? 3.7 [2 ws 3] 0.0 ? ? 0.25 t c ? 3.7 [ws 4] 0.0 ? 111 wr deassertion to data high impedance ? 0.25 t c + 0.2 [1 ws 3] ?2.3ns 1.25 t c + 0.2 [4 ws 7] ?10.6 2.25 t c + 0.2 [ws 8] ?18.9 112 previous rd deassertion to data active (write) ? 1.25 t c ? 4.0 [1 ws 3] 6.4 ? ns 2.25 t c ? 4.0 [4 ws 7] 14.7 ? 3.25 t c ? 4.0 [ws 8] 23.1 ? 113 rd deassertion time 0.75 t c ? 4.0 [1 ws 3] 2.2 ? ns 1.75 t c ? 4.0 [4 ws 7] 10.6 ? ns 2.75 t c ? 4.0 [ws 8] 18.9 ? ns table 3-8 sram read and write accesses 1 (continued) no. characteristics symbol expression 2 min max unit
DSP56366 technical data, rev. 3.1 3-14 freescale semiconductor 114 wr deassertion time 0.5 t c ? 4.0 [ws = 1] 0.2 ? ns t c ? 2.0 [2 ws 3] 6.3 ? ns 2.5 t c ? 4.0 [4 ws 7] 16.8 ? ns 3.5 t c ? 4.0 [ws 8] 25.2 ? ns 115 address valid to rd assertion 0.5 t c ? 4.0 0.2 ? ns 116 rd assertion pulse width (ws + 0.25) t c ? 4.0 6.4 ? ns 117 rd deassertion to address not valid 0.25 t c ? 2 .0 [1 ws 3] 0.1 ? ns 1.25 t c ? 2.0 [4 ws 7] 8.4 ? ns 2.25 t c ? 2.0 [ws 8] 16.7 ? ns 118 ta setup before rd or wr deassertion 4 0.25 t c + 2.0 4.1 ? ns 119 ta hold after rd or wr deassertion 0.0 ? ns 1 all timings for 100 mhz are measured from 0.5 vcc to .05 vcc 2 ws is the number of wait states specified in the bcr. 3 timings 100, 107 are guaranteed by design, not tested. 4 in the case of ta negation: timing 118 is relative to the deassertion edge of rd or wr were ta to remain active table 3-8 sram read and write accesses 1 (continued) no. characteristics symbol expression 2 min max unit
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-15 figure 3-9 sram read access figure 3-10 sram write access a0?a17 rd wr d0?d23 aa0?aa2 115 105 106 113 104 116 117 100 aa0468 ta 119 data in 118 a0?a17 wr rd data out d0?d23 aa0?aa2 100 102 101 107 114 108 109 103 ta 119 118
DSP56366 technical data, rev. 3.1 3-16 freescale semiconductor 3.10.2 dram timing the selection guides provided in figure 3-11 and figure 3-14 should be used for primary selection only. final selection should be ba sed on the timing provided in the following tables. as an example, the selection guide suggests that 4 wait states must be used for 100 mhz operation when using page mode dram. however, by using the information in the appropriat e table, a designer may choose to evaluate whether fewer wait states mig ht be used by determining which timing pr events operation at 100 mhz, running the chip at a slightly lower frequency (e.g., 95 mhz), using faster dram (if it become s available), and control factors such as capacitive and resistive lo ad to improve overall system performance. figure 3-11 dram page mode wait states selection guide chip frequency (mhz) dram type (trac ns) 100 80 70 60 40 66 80 100 1 wait states 2 wait states 3 wait states 4 wait states notes this figure should be use for primary selection. for exact and detailed timings see the following tables. aa0472 50 120
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-17 table 3-9 dram page mode timings, one wait state (low-power applications) 1, 2, 3 no. characteristics symbol expression 20 mhz 4 30 mhz 4 unit min max min max 131 page mode cycle time for two consecutive accesses of the same direction page mode cycle time for mixed (read and write) accesses t pc 2 t c 1.25 t c 100.0 62.5 ? ? 66.7 41.7 ? ? ns 132 cas assertion to data valid (read) t cac t c ? 7.5 ? 42.5 ? 25.8 ns 133 column address valid to data valid (read) t aa 1.5 t c ? 7.5 ? 67.5 ? 42.5 ns 134 cas deassertion to data not valid (read hold time) t off 0.0 ? 0.0 ? ns 135 last cas assertion to ras deassertion t rsh 0.75 t c ? 4.0 33.5 ? 21.0 ? ns 136 previous cas deassertion to ras deassertion t rhcp 2 t c ? 4.0 96.0 ? 62.7 ? ns 137 cas assertion pulse width t cas 0.75 t c ? 4.0 33.5 ? 21.0 ? ns 138 last cas deassertion to ras deassertion 5 ? brw[1:0] = 00 ? brw[1:0] = 01 ? brw[1:0] = 10 ? brw[1:0] = 11 t crp 1.75 t c ? 6.0 3.25 t c ? 6.0 4.25 t c ? 6.0 6.25 t c ? 6.0 81.5 156.5 206.5 306.5 ? ? ? ? 52.3 102.2 135.5 202.1 ? ? ? ? ns 139 cas deassertion pulse width t cp 0.5 t c ? 4.0 21.0 ? 12.7 ? ns 140 column address valid to cas assertion t asc 0.5 t c ? 4.0 21.0 ? 12.7 ? ns 141 cas assertion to column address not valid t cah 0.75 t c ? 4.0 33.5 ? 21.0 ? ns 142 last column address valid to ras deassertion t ral 2 t c ? 4.0 96.0 ? 62.7 ? ns 143 wr deassertion to cas assertion t rcs 0.75 t c ? 3.8 33.7 ? 21.2 ? ns 144 cas deassertion to wr assertion t rch 0.25 t c ? 3.7 8.8 ? 4.6 ? ns 145 cas assertion to wr deassertion t wch 0.5 t c ? 4.2 20.8 ? 12.5 ? ns 146 wr assertion pulse widt h t wp 1.5 t c ? 4.5 70.5 ? 45.5 ? ns 147 last wr assertion to ras deassertion t rwl 1.75 t c ? 4.3 83.2 ? 54.0 ? ns 148 wr assertion to cas deassertion t cwl 1.75 t c ? 4.3 83.2 ? 54.0 ? ns 149 data valid to cas assertion (write) t ds 0.25 t c ? 4.0 8.5 ? 4.3 ? ns
DSP56366 technical data, rev. 3.1 3-18 freescale semiconductor 150 cas assertion to data not valid (write) t dh 0.75 t c ? 4.0 33.5 ? 21.0 ? ns 151 wr assertion to cas assertion t wcs t c ? 4.3 45.7 ? 29.0 ? ns 152 last rd assertion to ras deassertion t roh 1.5 t c ? 4.0 71.0 ? 46.0 ? ns 153 rd assertion to data valid t ga t c ? 7.5 ? 42.5 ? 25.8 ns 154 rd deassertion to data not valid 6 t gz 0.0 ? 0.0 ? ns 155 wr assertion to data active 0.75 t c ? 0.3 37.2 ? 24.7 ? ns 156 wr deassertion to data high impedance 0.25 t c ? 12.5 ? 8.3 ns 1 the number of wait states for page mode access is specified in the dcr. 2 the refresh period is specified in the dcr. 3 all the timings are calculated for the worst case. some of the timings are better for specific cases (e.g., t pc equals 2 t c for read-after-read or write-after-write sequences). 4 reduced dsp clock speed allows use of p age mode dram with one wait state (see figure 3-14 .). 5 brw[1:0] (dram control register bits) de fines the number of wait states that should be inserted in each dram out-of-page access. 6 rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz . table 3-10 dram page mode timings, two wait states 1, 2, 3, 4 no. characteristics symbol expression 5 66 mhz 80 mhz unit min max min max 131 page mode cycle time for two consecutive accesses of the same direction page mode cycle time for mixed (read and write) accesses t pc 2 t c 1.25 t c 45.4 41.1 ? ? 37.5 34.4 ? ? ns 132 cas assertion to data valid (read) t cac 1.5 t c ? 7.5 1.5 t c ? 6.5 ? ? 15.2 ? ? ? ? 12.3 ns ns 133 column address valid to data valid (read) t aa 2.5 t c ? 7.5 2.5 t c ? 6.5 ? ? 30.4 ? ? ? ? 24.8 ns ns 134 cas deassertion to data not valid (read hold time) t off 0.0 ? 0.0 ? ns 135 last cas assertion to ras deassertion t rsh 1.75 t c ? 4.0 22.5 ? 17.9 ? ns 136 previous cas deassertion to ras deassertion t rhcp 3.25 t c ? 4.0 45.2 ? 36.6 ? ns 137 cas assertion pulse width t cas 1.5 t c ? 4.0 18.7 ? 14.8 ? ns table 3-9 dram page mode timings, on e wait state (low-power applications) 1, 2, 3 (continued) no. characteristics symbol expression 20 mhz 4 30 mhz 4 unit min max min max
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-19 138 last cas deassertion to ras deassertion 6 ? brw[1:0] = 00 ? brw[1:0] = 01 ? brw[1:0] = 10 ? brw[1:0] = 11 t crp 2.0 t c ? 6.0 3.5 t c ? 6.0 4.5 t c ? 6.0 6.5 t c ? 6.0 24.4 47.2 62.4 92.8 ? ? ? ? 19.0 37.8 50.3 75.3 ? ? ? ? ns 139 cas deassertion pulse width t cp 1.25 t c ? 4.0 14.9 ? 11.6 ? ns 140 column address valid to cas assertion t asc t c ? 4.0 11.2 ? 8.5 ? ns 141 cas assertion to column address not valid t cah 1.75 t c ? 4.0 22.5 ? 17.9 ? ns 142 last column address valid to ras deassertion t ral 3 t c ? 4.0 41.5 ? 33.5 ? ns 143 wr deassertion to cas assertion t rcs 1.25 t c ? 3.8 15.1 ? 11.8 ? ns 144 cas deassertion to wr assertion t rch 0.5 t c ? 3.7 3.9 ? 2.6 ? ns 145 cas assertion to wr deassertion t wch 1.5 t c ? 4.2 18.5 ? 14.6 ? ns 146 wr assertion pulse width t wp 2.5 t c ? 4.5 33.5 ? 26.8 ? ns 147 last wr assertion to ras deassertion t rwl 2.75 t c ? 4.3 33.4 ? 26.8 ? ns 148 wr assertion to cas deassertion t cwl 2.5 t c ? 4.3 33.6 ? 27.0 ? ns 149 data valid to cas assertion (write) t ds 0.25 t c ? 3.7 0.25 t c ? 3.0 0.1 ? ? ? ? 0.1 ? ? ns 150 cas assertion to data not valid (write) t dh 1.75 t c ? 4.0 22.5 ? 17.9 ? ns 151 wr assertion to cas assertion t wcs t c ? 4.3 10.9 ? 8.2 ? ns 152 last rd assertion to ras deassertion t roh 2.5 t c ? 4.0 33.9 ? 27.3 ? ns 153 rd assertion to data valid t ga 1.75 t c ? 7.5 1.75 t c ? 6.5 ? ? 19.0 ? ? ? ? 15.4 ns 154 rd deassertion to data not valid 7 t gz 0.0 ? 0.0 ? ns 155 wr assertion to data active 0.75 t c ? 0.3 11.1 ? 9.1 ? ns 156 wr deassertion to data high impedance 0.25 t c ?3.8?3.1ns 1 the number of wait states for page mode access is specified in the dcr. 2 the refresh period is specified in the dcr. 3 the asynchronous delays specified in the expressions are valid for DSP56366. 4 there are no drams fast enough to fit to two wait states page mode @ 100mhz (see figure 3-11 ) table 3-10 dram page mode timings, two wait states 1, 2, 3, 4 (continued) no. characteristics symbol expression 5 66 mhz 80 mhz unit min max min max
DSP56366 technical data, rev. 3.1 3-20 freescale semiconductor 5 all the timings are calculated for the worst case. some of the timings are better for specific cases (e.g., t pc equals 3 t c for read-after-read or write-after-write sequences). 6 brw[1:0] (dram control register bits) defines the number of wait states that should be in serted in each dram out-of-page access. 7 rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz. table 3-11 dram page mode timings, three wait states 1, 2, 3 no. characteristics symbol expression 4 min max unit 131 page mode cycle time for two consecutive accesses of the same direction page mode cycle time for mixed (read and write) accesses t pc 2 t c 1.25 t c 40.0 35.0 ? ? ns 132 cas assertion to data valid (read) t cac 2 t c ? 7.0 ? 13.0 ns 133 column address valid to data valid (read) t aa 3 t c ? 7.0 ? 23.0 ns 134 cas deassertion to data not valid (read hold time) t off 0.0 ? ns 135 last cas assertion to ras deassertion t rsh 2.5 t c ? 4.0 21.0 ? ns 136 previous cas deassertion to ras deassertion t rhcp 4.5 t c ? 4.0 41.0 ? ns 137 cas assertion pulse width t cas 2 t c ? 4.0 16.0 ? ns 138 last cas deassertion to ras assertion 5 ? brw[1:0] = 00 ? brw[1:0] = 01 ? brw[1:0] = 10 ? brw[1:0] = 11 t crp 2.25 t c ? 6.0 3.75 t c ? 6.0 4.75 t c ? 6.0 6.75 t c ? 6.0 ? ? 41.5 61.5 ? ? ? ? ns 139 cas deassertion pulse width t cp 1.5 t c ? 4.0 11.0 ? ns 140 column address valid to cas assertion t asc t c ? 4.0 6.0 ? ns 141 cas assertion to column address not valid t cah 2.5 t c ? 4.0 21.0 ? ns 142 last column address valid to ras deassertion t ral 4 t c ? 4.0 36.0 ? ns 143 wr deassertion to cas assertion t rcs 1.25 t c ? 4.0 8.5 ? ns 144 cas deassertion to wr assertion t rch 0.75 t c ? 4.0 3.5 ? ns 145 cas assertion to wr deassertion t wch 2.25 t c ? 4.2 18.3 ? ns 146 wr assertion pulse width t wp 3.5 t c ? 4.5 30.5 ? ns 147 last wr assertion to ras deassertion t rwl 3.75 t c ? 4.3 33.2 ? ns 148 wr assertion to cas deassertion t cwl 3.25 t c ? 4.3 28.2 ? ns 149 data valid to cas assertion (write) t ds 0.5 t c ? 4.0 1.0 ? ns
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-21 150 cas assertion to data not valid (write) t dh 2.5 t c ? 4.0 21.0 ? ns 151 wr assertion to cas assertion t wcs 1.25 t c ? 4.3 8.2 ? ns 152 last rd assertion to ras deassertion t roh 3.5 t c ? 4.0 31.0 ? ns 153 rd assertion to data valid t ga 2.5 t c ? 7.0 ? 18.0 ns 154 rd deassertion to data not valid 6 t gz 0.0 ? ns 155 wr assertion to data active 0.75 t c ? 0.3 7.2 ? ns 156 wr deassertion to data high impedance 0.25 t c ?2.5ns 1 the number of wait states for page mode access is specified in the dcr. 2 the refresh period is specified in the dcr. 3 the asynchronous delays specified in the expressions are valid for DSP56366. 4 all the timings are calculated for the worst case. some of the timings are better fo r specific ca ses (e.g., t pc equals 4 t c for read-after-read or write-after-write sequences). 5 brw[1:0] (dram control register bits) de fines the number of wait states that should be inserted in each dram out-of page-access. 6 rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz . table 3-12 dram page mode timings, four wait states 1, 2, 3 no. characteristics symbol expression 4 min max unit 131 page mode cycle time for two consecutive accesses of the same direction. page mode cycle time for mixed (read and write) accesses t pc 5 t c 4.5 t c 41.7 37.5 ? ? ns 132 cas assertion to data valid (read) t cac 2.75 t c ? 7.0 ? 15.9 ns 133 column address valid to data valid (read) t aa 3.75 t c ? 7.0 ? 24.2 ns 134 cas deassertion to data not valid (read hold time) t off 0.0 ? ns 135 last cas assertion to ras deassertion t rsh 3.5 t c ? 4.0 25.2 ? ns 136 previous cas deassertion to ras deassertion t rhcp 6 t c ? 4.0 46.0 ? ns 137 cas assertion pulse width t cas 2.5 t c ? 4.0 16.8 ? ns 138 last cas deassertion to ras assertion 5 ? brw[1:0] = 00 ? brw[1:0] = 01 ? brw[1:0] = 10 ? brw[1:0] = 11 t crp 2.75 t c ? 6.0 4.25 t c ? 6.0 5.25 t c ? 6.0 7.25 t c ? 6.0 ? ? 37.7 54.4 ? ? ? ? ns 139 cas deassertion pulse width t cp 2 t c ? 4.0 12.7 ? ns table 3-11 dram page mode timings, three wait states 1, 2, 3 (continued) no. characteristics symbol expression 4 min max unit
DSP56366 technical data, rev. 3.1 3-22 freescale semiconductor 140 column address valid to cas assertion t asc t c ? 4.0 4.3 ? ns 141 cas assertion to column address not valid t cah 3.5 t c ? 4.0 25.2 ? ns 142 last column address valid to ras deassertion t ral 5 t c ? 4.0 37.7 ? ns 143 wr deassertion to cas assertion t rcs 1.25 t c ? 4.0 6.4 ? ns 144 cas deassertion to wr assertion t rch 1.25 t c ? 4.0 6.4 ? ns 145 cas assertion to wr deassertion t wch 3.25 t c ? 4.2 22.9 ? ns 146 wr assertion pulse width t wp 4.5 t c ? 4.5 33.0 ? ns 147 last wr assertion to ras deassertion t rwl 4.75 t c ? 4.3 35.3 ? ns 148 wr assertion to cas deassertion t cwl 3.75 t c ? 4.3 26.9 ? ns 149 data valid to cas assertion (write) t ds 0.5 t c ? 4.0 0.2 ? ns 150 cas assertion to data not valid (write) t dh 3.5 t c ? 4.0 25.2 ? ns 151 wr assertion to cas assertion t wcs 1.25 t c ? 4.3 6.1 ? ns 152 last rd assertion to ras deassertion t roh 4.5 t c ? 4.0 33.5 ? ns 153 rd assertion to data valid t ga 3.25 t c ? 7.0 ? 20.1 ns 154 rd deassertion to data not valid 6 t gz 0.0 ? ns 155 wr assertion to data active 0.75 t c ? 0.3 5.9 ? ns 156 wr deassertion to data high impedance 0.25 t c ?2.1 ns 1 the number of wait states for page mode access is specified in the dcr. 2 the refresh period is specified in the dcr. 3 the asynchronous delays specified in the expressions are valid for DSP56366 . 4 all the timings are calculated for the worst case. some of the timings are better fo r specific cases (e.g., t pc equals 3 t c for read-after-read or write-after-write sequences). 5 brw[1:0] (dram control register bits) defines the number of wait states that should be in serted in each dram out-of-page access. 6 rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz . table 3-12 dram page mode timings, four wait states 1, 2, 3 (continued) no. characteristics symbol expression 4 min max unit
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-23 figure 3-12 dram page mode write accesses ras cas a0?a17 wr rd d0?d23 column row data out data out data out last column column add address address address 136 135 131 139 141 137 140 142 147 144 151 148 146 155 156 150 138 145 143 149 aa0473
DSP56366 technical data, rev. 3.1 3-24 freescale semiconductor figure 3-13 dram page mode read accesses ras cas a0?a17 wr rd d0?d23 column last column column row data in data in data in add address address address 136 135 131 137 140 141 142 143 152 133 153 132 138 139 134 154 aa0474
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-25 figure 3-14 dram out-of-page wait states selection guide table 3-13 dram out-of-page and refresh timings, four wait states 1, 2 no. characteristics 3 symbol expression 20 mhz 4 30 mhz 4 unit min max min max 157 random read or write cycle time t rc 5 t c 250.0 ? 166.7 ? ns 158 ras assertion to data valid (read) t rac 2.75 t c ? 7.5 ? 130.0 ? 84.2 ns 159 cas assertion to data valid (read) t cac 1.25 t c ? 7.5 ? 55.0 ? 34.2 ns 160 column address valid to data valid (read) t aa 1.5 t c ? 7.5 ? 67.5 ? 42.5 ns 161 cas deassertion to data not valid (read hold time) t off 0.0 ? 0.0 ? ns 162 ras deassertion to ras assertion t rp 1.75 t c ? 4.0 83.5 ? 54.3 ? ns 163 ras assertion pulse width t ras 3.25 t c ? 4.0 158.5 ? 104.3 ? ns 164 cas assertion to ras deassertion t rsh 1.75 t c ? 4.0 83.5 ? 54.3 ? ns chip frequency (mhz) dram type (trac ns) 100 80 70 50 66 80 100 4 wait states 8 wait states 11 wait states 15 wait states notes this figure should be use for primary selection. for exact and detailed timings see the following tables. 60 40 120 aa0475
DSP56366 technical data, rev. 3.1 3-26 freescale semiconductor 165 ras assertion to cas deassertion t csh 2.75 t c ? 4.0 133.5 ? 87.7 ? ns 166 cas assertion pulse width t cas 1.25 t c ? 4.0 58.5 ? 37.7 ? ns 167 ras assertion to cas assertion t rcd 1.5 t c 2 73.0 77.0 48.0 52.0 ns 168 ras assertion to co lumn address valid t rad 1.25 t c 2 60.5 64.5 39.7 43.7 ns 169 cas deassertion to ras assertion t crp 2.25 t c ? 4.0 108.5 ? 71.0 ? ns 170 cas deassertion pulse width t cp 1.75 t c ? 4.0 83.5 ? 54.3 ? ns 171 row address valid to ras assertion t asr 1.75 t c ? 4.0 83.5 ? 54.3 ? ns 172 ras assertion to row address not valid t rah 1.25 t c ? 4.0 58.5 ? 37.7 ? ns 173 column address valid to cas assertion t asc 0.25 t c ? 4.0 8.5 ? 4.3 ? ns 174 cas assertion to colu mn address not valid t cah 1.75 t c ? 4.0 83.5 ? 54.3 ? ns 175 ras assertion to colu mn address not valid t ar 3.25 t c ? 4.0 158.5 ? 104.3 ? ns 176 column address valid to ras deassertion t ral 2 t c ? 4.0 96.0 ? 62.7 ? ns 177 wr deassertion to cas assertion t rcs 1.5 t c ? 3.8 71.2 ? 46.2 ? ns 178 cas deassertion to wr assertion t rch 0.75 t c ? 3.7 33.8 ? 21.3 ? ns 179 ras deassertion to wr assertion t rrh 0.25 t c ? 3.7 8.8 ? 4.6 ? ns 180 cas assertion to wr deassertion t wch 1.5 t c ? 4.2 70.8 ? 45.8 ? ns 181 ras assertion to wr deassertion t wcr 3 t c ? 4.2 145.8 ? 95.8 ? ns 182 wr assertion pulse width t wp 4.5 t c ? 4.5 220.5 ? 145.5 ? ns 183 wr assertion to ras deassertion t rwl 4.75 t c ? 4.3 233.2 ? 154.0 ? ns 184 wr assertion to cas deassertion t cwl 4.25 t c ? 4.3 208.2 ? 137.4 ? ns 185 data valid to cas assertion (write) t ds 2.25 t c ? 4.0 108.5 ? 71.0 ? ns 186 cas assertion to data not valid (write) t dh 1.75 t c ? 4.0 83.5 ? 54.3 ? ns 187 ras assertion to data not valid (write) t dhr 3.25 t c ? 4.0 158.5 ? 104.3 ? ns 188 wr assertion to cas assertion t wcs 3 t c ? 4.3 145.7 ? 95.7 ? ns 189 cas assertion to ras assertion (refresh) t csr 0.5 t c ? 4.0 21.0 ? 12.7 ? ns 190 ras deassertion to cas assertion (refresh) t rpc 1.25 t c ? 4.0 58.5 ? 37.7 ? ns table 3-13 dram out-of-page and refresh timings, four wait states 1, 2 (continued) no. characteristics 3 symbol expression 20 mhz 4 30 mhz 4 unit min max min max
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-27 191 rd assertion to ras deassertion t roh 4.5 t c ? 4.0 221.0 ? 146.0 ? ns 192 rd assertion to data valid t ga 4 t c ? 7.5 ? 192.5 ? 125.8 ns 193 rd deassertion to data not valid 3 t gz 0.0 ? 0.0 ? ns 194 wr assertion to data active 0.75 t c ? 0.3 37.2 ? 24.7 ? ns 195 wr deassertion to data high impedance 0.25 t c ? 12.5 ? 8.3 ns 1 the number of wait states for out of page access is specified in the dcr. 2 the refresh period is specified in the dcr. 3 rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz . 4 reduced dsp clock speed allows use of dram ou t-of-page access with four wait states (see figure 3-17 .). table 3-14 dram out-of-page and refresh timings, eight wait states 1, 2 no. characteristics 3 symbol expression 4 66 mhz 80 mhz unit min max min max 157 random read or write cycle time t rc 9 t c 136.4 ? 112.5 ? ns 158 ras assertion to data valid (read) t rac 4.75 t c ? 7.5 4.75 t c ? 6.5 ? ? 64.5 ? ? ? ? 52.9 ns 159 cas assertion to data valid (read) t cac 2.25 t c ? 7.5 2.25 t c ? 6.5 ? ? 26.6 ? ? ? ? 21.6 ns 160 column address valid to data valid (read) t aa 3 t c ? 7.5 3 t c ? 6.5 ? ? 40.0 ? ? ? ? 31.0 ns 161 cas deassertion to data not valid (read hold time) t off 0.0 ? 0.0 ? ns 162 ras deassertion to ras assertion t rp 3.25 t c ? 4.0 45.2 ? 36.6 ? ns 163 ras assertion pulse width t ras 5.75 t c ? 4.0 83.1 ? 67.9 ? ns 164 cas assertion to ras deassertion t rsh 3.25 t c ? 4.0 45.2 ? 36.6 ? ns 165 ras assertion to cas deassertion t csh 4.75 t c ? 4.0 68.0 ? 55.5 ? ns 166 cas assertion pulse width t cas 2.25 t c ? 4.0 30.1 ? 24.1 ? ns 167 ras assertion to cas assertion t rcd 2.5 t c 2 35.9 39.9 29.3 33.3 ns 168 ras assertion to column address valid t rad 1.75 t c 2 24.5 28.5 19.9 23.9 ns table 3-13 dram out-of-page and refresh timings, four wait states 1, 2 (continued) no. characteristics 3 symbol expression 20 mhz 4 30 mhz 4 unit min max min max
DSP56366 technical data, rev. 3.1 3-28 freescale semiconductor 169 cas deassertion to ras assertion t crp 4.25 t c ? 4.0 59.8 ? 49.1 ? ns 170 cas deassertion pulse width t cp 2.75 t c ? 4.0 37.7 ? 30.4 ? ns 171 row address valid to ras assertion t asr 3.25 t c ? 4.0 45.2 ? 36.6 ? ns 172 ras assertion to row address not valid t rah 1.75 t c ? 4.0 22.5 ? 17.9 ? ns 173 column address valid to cas assertion t asc 0.75 t c ? 4.0 7.4 ? 5.4 ? ns 174 cas assertion to column address not valid t cah 3.25 t c ? 4.0 45.2 ? 36.6 ? ns 175 ras assertion to column address not valid t ar 5.75 t c ? 4.0 83.1 ? 67.9 ? ns 176 column address valid to ras deassertion t ral 4 t c ? 4.0 56.6 ? 46.0 ? ns 177 wr deassertion to cas assertion t rcs 2 t c ? 3.8 26.5 ? 21.2 ? ns 178 cas deassertion to wr 5 assertion t rch 1.25 t c ? 3.7 15.2 ? 11.9 ? ns 179 ras deassertion to wr 5 assertion t rrh 0.25 t c ? 3.7 0.25 t c ? 3.0 0.1 ? ? ? ? 0.1 ? ? ns 180 cas assertion to wr deassertion t wch 3 t c ? 4.2 41.3 ? 33.3 ? ns 181 ras assertion to wr deassertion t wcr 5.5 t c ? 4.2 79.1 ? 64.6 ? ns 182 wr assertion pulse width t wp 8.5 t c ? 4.5 124.3 ? 101.8 ? ns 183 wr assertion to ras deassertion t rwl 8.75 t c ? 4.3 128.3 ? 105.1 ? ns 184 wr assertion to cas deassertion t cwl 7.75 t c ? 4.3 113.1 ? 92.6 ? ns 185 data valid to cas assertion (write) t ds 4.75 t c ? 4.0 68.0 ? 55.4 ? ns 186 cas assertion to data not valid (write) t dh 3.25 t c ? 4.0 45.2 ? 36.6 ? ns 187 ras assertion to data not valid (write) t dhr 5.75 t c ? 4.0 83.1 ? 67.9 ? ns 188 wr assertion to cas assertion t wcs 5.5 t c ? 4.3 79.0 ? 64.5 ? ns 189 cas assertion to ras assertion (refresh) t csr 1.5 t c ? 4.0 18.7 ? 14.8 ? ns 190 ras deassertion to cas assertion (refresh) t rpc 1.75 t c ? 4.0 22.5 ? 17.9 ? ns 191 rd assertion to ras deassertion t roh 8.5 t c ? 4.0 124.8 ? 102.3 ? ns 192 rd assertion to data valid t ga 7.5 t c ? 7.5 7.5 t c ? 6.5 ? ? 106.1 ? ? ? ? 87.3 ns table 3-14 dram out-of-page and refresh timings, eight wait states 1, 2 (continued) no. characteristics 3 symbol expression 4 66 mhz 80 mhz unit min max min max
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-29 193 rd deassertion to data not valid 4 t gz 0.0 0.0 ? 0.0 ? ns 194 wr assertion to data active 0.75 t c ? 0.3 11.1 ? 9.1 ? ns 195 wr deassertion to data high impedance 0.25 t c ?3.8?3.1ns 1 the number of wait states for out-of -page access is specified in the dcr. 2 the refresh period is specified in the dcr. 3 rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz . 4 the asynchronous delays specified in the expressions are valid for DSP56366. 5 either t rch or t rrh must be satisf ied for read cycles. table 3-15 dram out-of-page and refresh timings, eleven wait states 1, 2 no. characteristics 3 symbol expression 4 min max unit 157 random read or write cycle time t rc 12 t c 120.0 ? ns 158 ras assertion to data valid (read) t rac 6.25 t c ? 7.0 ? 55.5 ns 159 cas assertion to data valid (read) t cac 3.75 t c ? 7.0 ? 30.5 ns 160 column address valid to data valid (read) t aa 4.5 t c ? 7.0 ? 38.0 ns 161 cas deassertion to data not valid (read hold time) t off 0.0 ? ns 162 ras deassertion to ras assertion t rp 4.25 t c ? 4.0 38.5 ? ns 163 ras assertion pulse width t ras 7.75 t c ? 4.0 73.5 ? ns 164 cas assertion to ras deassertion t rsh 5.25 t c ? 4.0 48.5 ? ns 165 ras assertion to cas deassertion t csh 6.25 t c ? 4.0 58.5 ? ns 166 cas assertion pulse width t cas 3.75 t c ? 4.0 33.5 ? ns 167 ras assertion to cas assertion t rcd 2.5 t c 4.0 21.0 29.0 ns 168 ras assertion to column address valid t rad 1.75 t c 4.0 13.5 21.5 ns 169 cas deassertion to ras assertion t crp 5.75 t c ? 4.0 53.5 ? ns 170 cas deassertion pulse width t cp 4.25 t c ? 4.0 38.5 ? ns 171 row address valid to ras assertion t asr 4.25 t c ? 4.0 38.5 ? ns 172 ras assertion to row address not valid t rah 1.75 t c ? 4.0 13.5 ? ns 173 column address valid to cas assertion t asc 0.75 t c ? 4.0 3.5 ? ns table 3-14 dram out-of-page and refresh timings, eight wait states 1, 2 (continued) no. characteristics 3 symbol expression 4 66 mhz 80 mhz unit min max min max
DSP56366 technical data, rev. 3.1 3-30 freescale semiconductor 174 cas assertion to column address not valid t cah 5.25 t c ? 4.0 48.5 ? ns 175 ras assertion to column address not valid t ar 7.75 t c ? 4.0 73.5 ? ns 176 column address valid to ras deassertion t ral 6 t c ? 4.0 56.0 ? ns 177 wr deassertion to cas assertion t rcs 3.0 t c ? 4.0 26.0 ? ns 178 cas deassertion to wr 5 assertion t rch 1.75 t c ? 4.0 13.5 ? ns 179 ras deassertion to wr 5 assertion t rrh 0.25 t c ? 2.0 0.5 ? ns 180 cas assertion to wr deassertion t wch 5 t c ? 4.2 45.8 ? ns 181 ras assertion to wr deassertion t wcr 7.5 t c ? 4.2 70.8 ? ns 182 wr assertion pulse width t wp 11.5 t c ? 4.5 110.5 ? ns 183 wr assertion to ras deassertion t rwl 11.75 t c ? 4.3 113.2 ? ns 184 wr assertion to cas deassertion t cwl 10.25 t c ? 4.3 103.2 ? ns 185 data valid to cas assertion (write) t ds 5.75 t c ? 4.0 53.5 ? ns 186 cas assertion to data not valid (write) t dh 5.25 t c ? 4.0 48.5 ? ns 187 ras assertion to data not valid (write) t dhr 7.75 t c ? 4.0 73.5 ? ns 188 wr assertion to cas assertion t wcs 6.5 t c ? 4.3 60.7 ? ns 189 cas assertion to ras assertion (refresh) t csr 1.5 t c ? 4.0 11.0 ? ns 190 ras deassertion to cas assertion (refresh) t rpc 2.75 t c ? 4.0 23.5 ? ns 191 rd assertion to ras deassertion t roh 11.5 t c ? 4.0 111.0 ? ns 192 rd assertion to data valid t ga 10 t c ? 7.0 ? 93.0 ns 193 rd deassertion to data not valid 3 t gz 0.0 ? ns 194 wr assertion to data active 0.75 t c ? 0.3 7.2 ? ns 195 wr deassertion to data high impedance 0.25 t c ?2.5ns 1 the number of wait states for out-of-page access is specified in the dcr. 2 the refresh period is specified in the dcr. 3 rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz . 4 the asynchronous delays specified in the expressions are valid for DSP56366. 5 either t rch or t rrh must be satisfied for read cycles. table 3-15 dram out-of-page and refresh timings, eleven wait states 1, 2 (continued) no. characteristics 3 symbol expression 4 min max unit
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-31 table 3-16 dram out-of-page and re fresh timings, fi fteen wait states 1, 2 no. characteristics 3 symbol expression min max unit 157 random read or write cycle time t rc 16 t c 133.3 ? ns 158 ras assertion to data valid (read) t rac 8.25 t c ? 5.7 ? 63.0 ns 159 cas assertion to data valid (read) t cac 4.75 t c ? 5.7 ? 33.9 ns 160 column address valid to data valid (read) t aa 5.5 t c ? 5.7 ? 40.1 ns 161 cas deassertion to data not valid (read hold time) t off 0.0 0.0 ? ns 162 ras deassertion to ras assertion t rp 6.25 t c ? 4.0 48.1 ? ns 163 ras assertion pulse width t ras 9.75 t c ? 4.0 77.2 ? ns 164 cas assertion to ras deassertion t rsh 6.25 t c ? 4.0 48.1 ? ns 165 ras assertion to cas deassertion t csh 8.25 t c ? 4.0 64.7 ? ns 166 cas assertion pulse width t cas 4.75 t c ? 4.0 35.6 ? ns 167 ras assertion to cas assertion t rcd 3.5 t c 2 27.2 31.2 ns 168 ras assertion to co lumn address valid t rad 2.75 t c 2 20.9 24.9 ns 169 cas deassertion to ras assertion t crp 7.75 t c ? 4.0 60.6 ? ns 170 cas deassertion pulse width t cp 6.25 t c ? 4.0 48.1 ? ns 171 row address valid to ras assertion t asr 6.25 t c ? 4.0 48.1 ? ns 172 ras assertion to row address not valid t rah 2.75 t c ? 4.0 18.9 ? ns 173 column address valid to cas assertion t asc 0.75 t c ? 4.0 2.2 ? ns 174 cas assertion to colu mn address not valid t cah 6.25 t c ? 4.0 48.1 ? ns 175 ras assertion to colu mn address not valid t ar 9.75 t c ? 4.0 77.2 ? ns 176 column address valid to ras deassertion t ral 7 t c ? 4.0 54.3 ? ns 177 wr deassertion to cas assertion t rcs 5 t c ? 3.8 37.9 ? ns 178 cas deassertion to wr 4 assertion t rch 1.75 t c ? 3.7 10.9 ? ns 179 ras deassertion to wr 5 assertion t rrh 0.25 t c ? 2.0 0.1 ? ns 180 cas assertion to wr deassertion t wch 6 t c ? 4.2 45.8 ? ns 181 ras assertion to wr deassertion t wcr 9.5 t c ? 4.2 75.0 ? ns 182 wr assertion pulse width t wp 15.5 t c ? 4.5 124.7 ? ns 183 wr assertion to ras deassertion t rwl 15.75 t c ? 4.3 126.9 ? ns
DSP56366 technical data, rev. 3.1 3-32 freescale semiconductor 184 wr assertion to cas deassertion t cwl 14.25 t c ? 4.3 114.4 ? ns 185 data valid to cas assertion (write) t ds 8.75 t c ? 4.0 68.9 ? ns 186 cas assertion to data not valid (write) t dh 6.25 t c ? 4.0 48.1 ? ns 187 ras assertion to data not valid (write) t dhr 9.75 t c ? 4.0 77.2 ? ns 188 wr assertion to cas assertion t wcs 9.5 t c ? 4.3 74.9 ? ns 189 cas assertion to ras assertion (refresh) t csr 1.5 t c ? 4.0 8.5 ? ns 190 ras deassertion to cas assertion (refresh) t rpc 4.75 t c ? 4.0 35.6 ? ns 191 rd assertion to ras deassertion t roh 15.5 t c ? 4.0 125.2 ? ns 192 rd assertion to data valid t ga 14 t c ? 5.7 ? 111.0 ns 193 rd deassertion to data not valid 3 t gz 0.0 ? ns 194 wr assertion to data active 0.75 t c ? 0.3 5.9 ? ns 195 wr deassertion to data high impedance 0.25 t c ?2.1ns 1 the number of wait states for out-of-page access is specified in the dcr. 2 the refresh period is specified in the dcr. 3 rd deassertion will always occur after cas deassertion; therefore, the restricted timing is t off and not t gz . 4 either t rch or t rrh must be satisfied for read cycles. table 3-16 dram out-of-page and refresh timings, fifteen wait states 1, 2 (continued) no. characteristics 3 symbol expression min max unit
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-33 figure 3-15 dram out-of-page read access ras cas a0?a17 wr rd d0?d23 data row address column address in 157 163 165 162 162 169 170 171 168 167 164 166 173 174 175 172 177 176 191 160 168 159 193 161 192 158 179 aa0476
DSP56366 technical data, rev. 3.1 3-34 freescale semiconductor figure 3-16 dram out-of-page write access ras cas a0?a17 wr rd d0?d23 data out column address row address 162 163 165 162 157 169 170 167 168 164 166 171 173 174 176 172 181 175 180 188 182 184 183 187 185 194 186 195 aa0477
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-35 figure 3-17 dram refresh access 3.10.3 arbitration timings table 3-17 asynchronous bus arbitration timing no. characteristics expression 120 mhz unit min max 250 bb assertion window from bg input negation. 2 .5* tc + 5 ? 25.8 ns 251 delay from bb assertion to bg assertion 2 * tc + 5 21.7 ? ns notes: 1. bit 13 in the omr register must be set to enter asynchronous arbitration mode 2. if asynchronous arbitration mode is active, none of the timings in table 3-17 is required. 3. in order to guarantee timings 250, and 251, it is recommended to assert bg inputs to different 56300 devices (on the same bus) in a non overlap manner as shown in figure 3-18 . ras cas wr 157 163 162 162 190 170 165 189 177 aa0478
DSP56366 technical data, rev. 3.1 3-36 freescale semiconductor figure 3-18 asynchronous bus arbitration timing figure 3-19 asynchronous bus arbitration timing background explanation for as ynchronous bus arbitration: the asynchronous bus arbitration is enabled by internal synchronization circuits on bg and bb inputs. these synchronization circuits add delay from the external signal until it is exposed to internal logic. as a result of this delay, a 56300 part may assume mastership and assert bb for some time after bg is negated. this is the reason for timing 250. once bb is asserted, there is a synchronization delay from bb assertion to the time this assertion is exposed to other 56300 componen ts which are poten tial masters on the same bus. if bg input is asserted before that time, a situation of bg asserted, and bb negated, may cause another 56300 component to assume mastership at the same time. ther efore some non-overlap period between one bg input active to another bg input active is required. timing 251 ensures that such a situation is avoided. bg1 bb 250 251 bg2 bg1 bg2 250+251
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-37 3.11 parallel host interface (hdi08) timing table 3-18 host interface (hdi08) timing 1, 2 no. characteristics 3 expression 120 mhz unit min max 317 read data strobe assertion width 4 hack read assertion width t c + 9.9 18.3 ? ns 318 read data strobe deassertion width 4 hack read deassertion width ?9.9?ns 319 read data strobe deassertion width 4 after ?last data register? reads 5,6 , or between two consecutive cv r, icr, or isr reads 7 hack deassertion width after ?l ast data register? reads 5 , 6 2.5 t c + 6.6 27.4 ? ns 320 write data strobe assertion width 8 hack write assertion width ? 13.2 ? ns 321 write data strobe deassertion width 8 hack write deassertion width ? after icr, cvr and ?last data register? writes 5 ? after ivr writes, or ? after txh:txm writes (with hbe=0), or ? after txl:txm writes (with hbe=1) 2.5 t c + 6.6 27.4 16.5 ? ? ns 322 has assertion width ?9.9?ns 323 has deassertion to data strobe assertion 9 ?0.0?ns 324 host data input setup time before write data strobe deassertion 8 host data input setup time before hack write deassertion ?9.9?ns 325 host data input hold time after write data strobe deassertion 8 host data input hold time after hack write deassertion ?3.3?ns 326 read data strobe assertion to outp ut data active from high impedance 4 hack read assertion to output data active from high impedance ?3.3?ns 327 read data strobe assertion to output data valid 4 hack read assertion to output data valid ? ? 24.2 ns 328 read data strobe deassertion to output data high impedance 4 hack read deassertion to output data high impedance ??9.9ns 329 output data hold time after read data strobe deassertion 4 output data hold time after hack read deassertion ?3.3?ns 330 hcs assertion to read data strobe deassertion 4 t c +9.9 18.2 ? ns 331 hcs assertion to write data strobe deassertion 8 ?9.9?ns 332 hcs assertion to output data valid ? ? 19.1 ns
DSP56366 technical data, rev. 3.1 3-38 freescale semiconductor 333 hcs hold time after data strobe deassertion 9 ?0.0?ns 334 address (ad7?ad0) setup time before has deassertion (hmux=1) ? 4.7 ? ns 335 address (ad7?ad0) hold time after has deassertion (hmux=1) ? 3.3 ? ns 336 a10?a8 (hmux=1), a2?a0 (hmux=0), hr/w setup time before data strobe assertion 9 ? read ?write ?0 4.7 ? ? ns 337 a10?a8 (hmux=1), a2?a0 (hmux=0), hr/w hold time after data strobe deassertion 9 ?3.3?ns 338 delay from read data strobe deassertion to host request assertion for ?last data register? read 4 , 5 , 10 t c 8.3 ? ns 339 delay from write data strobe deassertio n to host request assertion for ?last data register? write 5 , 8 , 10 2 t c 16.7 ? ns 340 delay from data strobe assertion to host request deassertion for ?last data register? read or write (hrod = 0) 5 , 9 , 10 ? ? 19.1 ns 341 delay from data strobe assertion to host request deassertion for ?last data register? read or write (hrod = 1, open drain host request) 5 , 9 , 10 , 11 ? ? 300.0 ns 342 delay from dma hack deassertion to horeq assertion ? for ?last data register? read 5 ? for ?last data register? write 5 ? for other cases 2 t c + 19.1 1.5 t c + 19.1 35.8 31.6 0.0 ? ? ? ns 343 delay from dma hack assertion to horeq deassertion ?hrod = 0 5 ? ? 20.2 ns 344 delay from dma hack assertion to horeq deassertion for ?last data register? read or write ? hrod = 1, open drain host request 5 , 11 ? ? 300.0 ns 1 see host port usage considerations in the DSP56366 user?s manual. 2 in the timing diagrams below, the controls pins are draw n as active low. the pin polarity is programmable. 3 v cc = 3.3 v 0.16 v; t j = ?40c to +110c, c l = 50 pf 4 the read data strobe is hrd in the dual data strobe mode and hds in the single data strobe mode. 5 the ?last data register? is the register at address $7, which is the last location to be read or written in data transfers. 6 this timing is applicable only if a read from the ?last data regi ster? is followed by a read from the rxl, rxm, or rxh register s without first polling rxdf or hreq bits, or waiting for the assertion of the horeq signal. 7 this timing is applicable only if two consecut ive reads from one of thes e registers are executed. 8 the write data strobe is hwr in the dual data stro be mode and hds in the single data strobe mode. 9 the data strobe is host read (hrd) or host write (hwr) in the d ual data strobe mode and host data strobe (hds) in the single data strobe mode. 10 the host request is horeq in the single host request m ode and hrrq and htrq in the double host request mode. 11 in this calculation, the host request signal is pulled up by a 4.7 k resistor in the open-drain mode. table 3-18 host interface (hdi08) timing 1, 2 (continued) no. characteristics 3 expression 120 mhz unit min max
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-39 figure 3-20 host interrupt vector register (ivr) read timing diagram figure 3-21 read timing diagram, non-multiplexed bus hack hd7?hd0 horeq 329 317 318 328 326 327 aa1105 hrd, hds ha0?ha2 hcs hd0?hd7 horeq, 327 332 319 318 317 330 329 337 336 328 326 338 341 340 333 aa0484 hrrq, htrq
DSP56366 technical data, rev. 3.1 3-40 freescale semiconductor figure 3-22 write timing diagram, non-multiplexed bus hwr, hds ha0?ha2 hcs hd0?hd7 horeq, hrrq, htrq 336 331 337 321 320 324 325 339 340 341 333 aa0485
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-41 figure 3-23 read timing di agram, multiplexed bus hrd, hds ha8?ha10 has had0?had7 horeq, hrrq, htrq address data 317 318 319 328 329 327 326 335 336 337 334 341 340 338 323 aa0486 322
DSP56366 technical data, rev. 3.1 3-42 freescale semiconductor figure 3-24 write timing diagram, multiplexed bus figure 3-25 host dma write timing diagram hwr, hds ha8?ha10 horeq, hrrq, htrq has had0?had7 address data 320 321 325 324 335 341 339 336 334 340 322 323 aa0487 horeq (output) hack (input) h0?h7 (input) data valid txh/m/l write 320 321 343 342 324 344 325
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-43 figure 3-26 host dma read timing diagram 3.12 serial host interface spi protocol timing table 3-19 serial host interface spi protocol timing no. characteristics 1 mode filter mode expression min max unit 140 tolerable spike width on clock or data in ? bypassed ? ? 0 ns narrow ? ? 50 ns wide ? ? 100 ns 141 minimum serial clock cycle = t spicc (min) master bypassed 6 t c +46 96 ? ns narrow 6 t c +152 202 ? ns wide 6 t c +223 273 ? ns 142 serial clock high period master bypassed 0.5 t spicc ?10 38 ? ns narrow 0.5 t spicc ?10 91 ? ns wide 0.5 t spicc ?10 126.5 ? ns slave bypassed 2.5 t c +12 32.8 ? ns narrow 2.5 t c +102 122.8 ? ns wide 2.5 t c +189 209.8 ? ns 326 317 318 327 328 329 data valid horeq (output) hack (input) h0-h7 (output) rxh read 343 342 342
DSP56366 technical data, rev. 3.1 3-44 freescale semiconductor 143 serial clock low period master bypassed 0.5 t spicc ?10 38 ? ns narrow 0.5 t spicc ?10 91 ? ns wide 0.5 t spicc ?10 126.5 ? ns slave bypassed 2.5 t c +12 32.8 ? ns narrow 2.5 t c +102 122.8 ? ns wide 2.5 t c +189 209.8 ? ns 144 serial clock rise/fall time master ? ? ? 10 ns slave ? ? ? 2000 ns 146 ss assertion to first sck edge cpha = 0 slave bypassed 3.5 t c +15 44.2 ? ns narrow 0 0 ? ns wide 0 0 ? ns cpha = 1 slave bypassed 10 10 ? ns narrow 0 0 ? ns wide 0 0 ? ns 147 last sck edge to ss not asserted slave bypassed 12 12 ? ns narrow 102 102 ? ns wide 189 189 ? ns 148 data input valid to sck edge (data input set-up time) master/slave bypassed 0 0 ? ns narrow max{(20-t c ), 0} 11.7 ? ns wide max{(40-t c ), 0} 31.7 ? ns 149 sck last sampling edge to data input not valid master/slave bypassed 2.5 t c +10 30.8 ? ns narrow 2.5 t c +30 50.8 ? ns wide 2.5 t c +50 70.8 ? ns 150 ss assertion to data out active slave ? 2 2 ? ns 151 ss deassertion to data high impedance 2 slave ? 9 ? 9 ns table 3-19 serial host interface spi protocol timing (continued) no. characteristics 1 mode filter mode expression min max unit
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-45 152 sck edge to data out valid (data out delay time) master/slave bypassed 2 t c +33 ? 49.7 ns narrow 2 t c +123 ? 139.7 ns wide 2 t c +210 ? 226.7 ns 153 sck edge to data out not valid (data out hold time) master/slave bypassed t c +5 13.3 ? ns narrow t c +55 63.3 ? ns wide t c +106 114.3 ? ns 154 ss assertion to data out valid (cpha = 0) slave ? t c +33 ? 41.3 ns 157 first sck sampling edge to hreq output deassertion slave bypassed 2.5 t c +30 ? 50.8 ns narrow 2.5 t c +120 ? 140.8 ns wide 2.5 t c +217 ? 237.8 ns 158 last sck sampling edge to hreq output not deasserted (cpha = 1) slave bypassed 2.5 t c +30 50.8 ? ns narrow 2.5 t c +80 100.8 ? ns wide 2.5 t c +136 156.8 ? ns 159 ss deassertion to hreq output not deasserted (cpha = 0) slave ? 2.5 t c +30 50.8 ? ns 160 ss deassertion pulse width (cpha = 0) slave ? t c +6 14.3 ? ns 161 hreq in assertion to first sck edge master bypassed 0.5 t spicc + 2.5 t c +43 111.8 ? ns narrow 0.5 t spicc + 2.5 t c +43 164.8 ? ns wide 0.5 t spicc + 2.5 t c +43 200.3 ? ns 162 hreq in deassertion to last sck sampling edge (hreq in set-up time) (cpha = 1) master ? 0 0 ? ns 163 first sck edge to hreq in not asserted (hreq in hold time) master ? 0 0 ? ns 1 v cc = 3.16 v 0.16 v; t j = ?40c to +110c, c l = 50 pf 2 periodically sampled, not 100% tested table 3-19 serial host interface spi protocol timing (continued) no. characteristics 1 mode filter mode expression min max unit
DSP56366 technical data, rev. 3.1 3-46 freescale semiconductor figure 3-27 spi mast er timing (cpha = 0) ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) valid mosi (output) msb valid lsb msb lsb hreq (input) 141 142 143 144 144 141 144 144 143 142 148 149 149 148 152 153 163 161 aa0271
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-47 figure 3-28 spi mast er timing (cpha = 1) ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) valid mosi (output) msb valid lsb msb lsb hreq (input) 141 142 143 144 144 141 144 144 143 142 148 148 149 152 153 163 161 162 149 aa0272
DSP56366 technical data, rev. 3.1 3-48 freescale semiconductor figure 3-29 spi slave timing (cpha = 0) ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) msb lsb msb lsb hreq (output) 141 142 143 144 144 141 144 144 143 142 154 150 152 153 148 149 159 157 153 151 valid valid 148 149 147 160 146 aa0273
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-49 figure 3-30 spi slave timing (cpha = 1) ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) msb lsb msb lsb hreq (output) 141 142 143 144 144 144 144 143 142 150 152 148 149 158 153 151 valid valid 148 147 146 152 149 157 aa0274
DSP56366 technical data, rev. 3.1 3-50 freescale semiconductor 3.13 serial host interface (shi) i 2 c protocol timing table 3-20 shi i 2 c protocol timing no. characteristics 1,2,3 symbol/ expression standard mode 4 fast mode 5 unit min max min max tolerable spike width on scl or sda filters bypassed ? ? 0 ? 0 ns narrow filters enabled ? 50 ? 50 ns wide filters enabled ? 100 ? 100 ns 171 scl clock frequency f scl ? 100 ? 400 khz 171 scl clock cycle t scl 10 ? 2.5 ? s 172 bus free time t buf 4.7 ? 1.3 ? s 173 start condition set-up time t su;sta 4.7 ? 0.6 ? s 174 start condition hold time t hd;sta 4.0 ? 0.6 ? s 175 scl low period t low 4.7 ? 1.3 ? s 176 scl high period t high 4.0 ? 1.3 ? s 177 scl and sda rise time t r ? 1000 20 + 0.1 c b 300 ns 178 scl and sda fall time t f ? 300 20 + 0.1 c b 300 ns 179 data set-up time t su;dat 250 ? 100 ? ns 180 data hold time t hd;dat 0.0 ? 0.0 0.9 s 181 dsp clock frequency f dsp mhz filters bypassed 10.6 ? 28.5 ? narrow filters enabled 11.8 ? 39.7 ? wide filters enabled 13.1 ? 61.0 ? 182 scl low to data out valid t vd;dat ? 3.4 ? 0.9 s 183 stop condition set-up time t su;sto 4.0 ? 0.6 ? s 184 hreq in deassertion to last scl edge (hreq in set-up time) t su;rqi 0.0 ? 0.0 ? ns
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-51 186 first scl sampling edge to hreq output deassertion t ng;rqo ns filters bypassed 2 t c + 30 ? 46.7 ? 46.7 narrow filters enabled 2 t c + 120 ? 136.7 ? 136.7 wide filters enabled 2 t c + 208 ? 224.7 ? 224.7 187 last scl edge to hreq output not deasserted t as;rqo ns filters bypassed 2 t c + 30 46.7 ? 46.7 ? narrow filters enabled 2 t c + 80 96.7 ? 96.7 ? wide filters enabled 2 t c + 135 151.6 ? 151.6 ? 188 hreq in assertion to first scl edge t as;rqi 0.5 t i 2 ccp - 0.5 t c - 21 ns filters bypassed 4440 ? 1041 ? narrow filters enabled 4373 ? 999 ? wide filters enabled 4373 ? 958 ? 189 first scl edge to hreq in not asserted (hreq in hold time) t ho;rqi 0.0 ? 0.0 ? ns 1 v cc = 3.16 v 0.16 v; t j = ?40c to +110c 2 pull-up resistor: r p (min) = 1.5 kohm 3 capacitive load: c b (max) = 400 pf 4 it is recommended to enable the wid e filters when operating in the i 2 c standard mode. 5 it is recommended to enable the narrow filters when operating in the i 2 c fast mode. table 3-20 shi i 2 c protocol timing (continued) no. characteristics 1,2,3 symbol/ expression standard mode 4 fast mode 5 unit min max min max
DSP56366 technical data, rev. 3.1 3-52 freescale semiconductor 3.13.1 programming the serial clock the programmed serial clock cycle, t i 2 ccp , is specified by the value of th e hdm[7:0] and hrs bits of the hckr (shi clock control register). the expression for t i 2 ccp is where hrs is the prescaler rate se lect bit. when hrs is clear ed, the fixed divide-by-eight prescaler is operational. when hrs is set, the prescaler is bypassed. hdm[7:0] are the divider modulus select bits. a divide ratio from 1 to 256 (hdm[7:0] = $00 to $ff) may be selected. in i 2 c mode, the user may select a value fo r the programmed seri al clock cycle from to the programmed serial clock cycle (t i 2 ccp ), scl rise time (t r ), and the filters sel ected should be chosen in order to achieve the desi red scl serial clock cycle (t scl ), as shown in table 3-21 . example: for dsp clock frequency of 120 mhz (i.e. t c = 8.33ns), operating in a standard mode i 2 c environment (f scl = 100 khz (i.e. t scl = 10 s), t r = 1000ns), with wide filters enabled: choosing hrs = 0 gives thus the hdm[7:0] value shoul d be programmed to $41 (=65). table 3-21 scl serial clock cycle (t scl ) generated as master filters bypassed t i 2 ccp + 2.5 t c + 45ns + t r narrow filters enabled t i 2 ccp + 2.5 t c + 135ns + t r wide filters enabled t i 2 ccp + 2.5 t c + 223ns + t r t i 2 ccp t [ c 2 hdm 7 : 0 [] ( 1 ) 71hrs ? () 1 + () + ] = 6t c if hdm 7 : 0 [] 02 and hrs $ 1 == 4096 t c if hdm 7 : 0 [] ff and hrs $ 0 == t i 2 ccp 10 s 2.5 8.33ns 223ns 1000ns ? ? ? 8756ns == hdm 7 : 0 [] 8756ns 2 ( 8.33ns 8 ) 1 64.67 = ? ? =
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-53 the resulting t i 2 ccp will be: figure 3-31 i 2 c timing t i 2 ccp t c 2 hdm 7 : 0 [] ( 1 ) 7 ( 1 ( hrs ) 1 ) + ? + [] = t i 2 ccp 8.33ns 2 65 ( 1 ) 7 ( 1 ( 0 ) 1 ) + ? + [] = t i 2 ccp 8.33ns 2 66 8 [] 8796.48ns == start scl hreq sda ack msb lsb stop 171 stop 173 176 175 177 178 180 179 172 186 182 183 189 174 188 184 187 aa0275
DSP56366 technical data, rev. 3.1 3-54 freescale semiconductor 3.14 enhanced serial audio interface timing table 3-22 enhanced serial audio interface timing no. characteristics 1, 2, 3 symbol expression min max condition 4 unit 430 clock cycle 5 t ssicc 4 t c 3 t c txc:max[3*tc; t454] 33.3 25.0 27.2 ? ? ? i ck x ck x ck ns 431 clock high period ? for internal clock ? for external clock ? 2 t c ? 10.0 1.5 t c 6.7 12.5 ? ? ns 432 clock low period ? for internal clock ? for external clock ? 2 t c ? 10.0 1.5 t c 6.7 12.5 ? ? ns 433 rxc rising edge to fsr out (bl) high ? ? ? ? 37.0 22.0 x ck i ck a ns 434 rxc rising edge to fsr out (bl) low ? ? ? ? 37.0 22.0 x ck i ck a ns 435 rxc rising edge to fsr out (wr) high 6 ??? ? 39.0 24.0 x ck i ck a ns 436 rxc rising edge to fsr out (wr) low 6 ??? ? 39.0 24.0 x ck i ck a ns 437 rxc rising edge to fsr out (wl) high ? ? ? ? 36.0 21.0 x ck i ck a ns 438 rxc rising edge to fsr out (wl) low ? ? ? ? 37.0 22.0 x ck i ck a ns 439 data in setup time before rxc (sck in synchronous mode) falling edge ??0.0 19.0 ? ? x ck i ck ns 440 data in hold time after rxc falling edge ? ? 5.0 3.0 ? ? x ck i ck ns 441 fsr input (bl, wr) high before rxc falling edge 6 ??23.0 1.0 ? ? x ck i ck a ns 442 fsr input (wl) high before rxc falling edge ??1.0 23.0 ? ? x ck i ck a ns 443 fsr input hold time after rxc falling edge ??3.0 0.0 ? ? x ck i ck a ns
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-55 444 flags input setup before rxc falling edge ??0.0 19.0 ? ? x ck i ck s ns 445 flags input hold time after rxc falling edge ??6.0 0.0 ? ? x ck i ck s ns 446 txc rising edge to fst out (bl) high ? ? ? ? 29.0 15.0 x ck i ck ns 447 txc rising edge to fst out (bl) low ? ? ? ? 31.0 17.0 x ck i ck ns 448 txc rising edge to fst out (wr) high 6 ??? ? 31.0 17.0 x ck i ck ns 449 txc rising edge to fst out (wr) low 6 ??? ? 33.0 19.0 x ck i ck ns 450 txc rising edge to fst out (wl) high ? ? ? ? 30.0 16.0 x ck i ck ns 451 txc rising edge to fst out (wl) low ? ? ? ? 31.0 17.0 x ck i ck ns 452 txc rising edge to data out enable from high impedance ??? ? 31.0 17.0 x ck i ck ns 453 txc rising edge to transmitter #0 drive enable assertion ??? ? 34.0 20.0 x ck i ck ns 454 txc rising edge to data out valid ? 23 + 0.5 t c 21.0 ? ? 27.2 21.0 x ck i ck ns 455 txc rising edge to data out high impedance 7 ??? ? 31.0 16.0 x ck i ck ns 456 txc rising edge to transmitter #0 drive enable deassertion 7 ??? ? 34.0 20.0 x ck i ck ns 457 fst input (bl, wr) setup time before txc falling edge 6 ??2.0 21.0 ? ? x ck i ck ns 458 fst input (wl) to data out enable from high impedance ? ? ? 27.0 ? ns 459 fst input (wl) to transmitter #0 drive enable assertion ? ? ? 31.0 ? ns table 3-22 enhanced serial audio interface timing (continued) no. characteristics 1, 2, 3 symbol expression min max condition 4 unit
DSP56366 technical data, rev. 3.1 3-56 freescale semiconductor 460 fst input (wl) setup time before txc falling edge ??2.0 21.0 ? ? x ck i ck ns 461 fst input hold time after txc falling edge ??4.0 0.0 ? ? x ck i ck ns 462 flag output valid after txc rising edge ? ? ? ? 32.0 18.0 x ck i ck ns 463 hckr/hckt clock cycle ? ? 40.0 ? ns 464 hckt input rising edge to txc output ? ? ? 27.5 ns 465 hckr input rising edge to rxc output ? ? ? 27.5 ns 1 v cc = 3.16 v 0.16 v; t j = ?40c to +110c, c l = 50 pf 2 i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that txc and rxc are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that txc and rxc are the same clock) 3 bl = bit length wl = word length wr = word length relative 4 txc(sckt pin) = transmit clock rxc(sckr pin) = receive clock fst(fst pin) = transmit frame sync fsr(fsr pin) = receive frame sync hckt(hckt pin) = transmit high frequency clock hckr(hckr pin) = receive high frequency clock 5 for the internal clock, the external clock cycle is defined by icyc and the esai control register. 6 the word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before firs t bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. 7 periodically sampled and not 100% tested table 3-22 enhanced serial audio interface timing (continued) no. characteristics 1, 2, 3 symbol expression min max condition 4 unit
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-57 figure 3-32 esai transmitter timing last bit see note txc (input/output) fst (bit) out fst (word) out data out transmitter #0 drive enable fst (bit) in fst (word) in flags out notes in network mode, output flag transitions can occur at the start of eac h time slot within the frame. in normal mode, the output flag state is asserted for the entire frame period. first bit 430 432 446 447 450 451 455 454 454 452 459 456 453 461 457 458 460 461 462 431 aa0490
DSP56366 technical data, rev. 3.1 3-58 freescale semiconductor figure 3-33 esai receiver timing figure 3-34 esai hckt timing rxc (input/output) fsr (bit) out fsr (word) out data in fsr (bit) in fsr (word) in flags in last bit first bit 430 432 433 437 438 440 439 443 441 442 443 445 444 431 434 aa0491 hckt sckt(output) 464 463
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-59 figure 3-35 esai hckr timing 3.15 digital audio transmitter timing figure 3-36 digital audio transmitter timing table 3-23 digital audio transmitter timing no. characteristic expression 120 mhz unit min max aci frequency (see note) 1 / (2 x t c )? 60mhz 220 aci period 2 t c 16.7 ? ns 221 aci high duration 0.5 t c 4.2 ? ns 222 aci low duration 0.5 t c 4.2 ? ns 223 aci rising edge to ado valid 1.5 t c ?12.5ns note: in order to assure proper operation of the dax, the aci frequency should be less than 1/2 of the DSP56366 internal clock frequency. for example, if the DSP56366 is running at 120 mhz internally, the aci frequency should be less than 60 mhz. hckr sckr (output) 465 463 aci ado 220 223 aa1280 221 222
DSP56366 technical data, rev. 3.1 3-60 freescale semiconductor 3.16 timer timing figure 3-37 tio timer event input restrictions 3.17 gpio timing table 3-24 timer timing no. characteristics expression 120 mhz unit min max 480 tio low 2 t c + 2.0 18.7 ? ns 481 tio high 2 t c + 2.0 18.7 ? ns note: v cc = 3.3 v 0.16 v; t j = ?40c to +110c, c l = 50 pf table 3-25 gpio timing no. characteristics 1 1 v cc = 3.3 v 0.16 v; t j = ?40c to +110c, c l = 50 pf expression min max unit 490 2 2 valid only when pll enabled with multiplication factor equal to one. extal edge to gpio out valid (gpio out delay time) ? 32.8 ns 491 extal edge to gpio out not valid (gpio out hold time) 4.8 ? ns 492 gpio in valid to extal edge (gpio in set-up time) 10.2 ? ns 493 extal edge to gpio in not valid (gpio in hold time) 1.8 ? ns 494 2 fetch to extal edge before gpio change 6.75 t c -1.8 54.5 ? ns 495 gpio out rise time ? ? 13 ns 496 gpio out fall time ? ? 13 ns tio 481 480 aa0492
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-61 figure 3-38 gpio timing 3.18 jtag timing table 3-26 jtag timing 1, 2 no. characteristics all frequencies unit min max 500 tck frequency of operation (1/(t c 3); maximum 22 mhz) 0.0 22.0 mhz 501 tck cycle time in crystal mode 45.0 ? ns 502 tck clock pulse width measured at 1.5 v 20.0 ? ns 503 tck rise and fall times 0.0 3.0 ns 504 boundary scan input data setup time 5.0 ? ns 505 boundary scan input data hold time 24.0 ? ns 506 tck low to output data valid 0.0 40.0 ns 507 tck low to output high impedance 0.0 40.0 ns 508 tms, tdi data setup time 5.0 ? ns valid gpio (input) gpio (output) extal (input) fetch the instruction move x0,x:(r0); x0 contains the new value of gpio and r0 contains the addre ss of gpio data register. a0?a17 490 491 492 494 493 gpio (output) 495 496
DSP56366 technical data, rev. 3.1 3-62 freescale semiconductor figure 3-39 test clock input timing diagram figure 3-40 boundary scan (jtag) timing diagram 509 tms, tdi data hold time 25.0 ? ns 510 tck low to tdo data valid 0.0 44.0 ns 511 tck low to tdo high impedance 0.0 44.0 ns notes: 1. 4. 1 v cc = 3.3 v 0.16 v; t j = ?40c to +110c, c l = 50 pf 2 all timings apply to once module data transfers because it uses the jtag port as an interface. table 3-26 jtag timing 1, 2 (continued) no. characteristics all frequencies unit min max tck (input) vm vm vih vil 501 502 502 503 503 aa0496 tck (input) data inputs data outputs data outputs data outputs vih vil input data valid output data valid output data valid 505 504 506 507 506 aa0497
DSP56366 technical data, rev. 3.1 freescale semiconductor 3-63 figure 3-41 test access port timing diagram tck (input) tdi (input) tdo (output) tdo (output) tdo (output) vih vil input data valid output data valid output data valid tms 508 509 510 511 510 aa0498
DSP56366 technical data, rev. 3.1 3-64 freescale semiconductor notes
DSP56366 technical data, rev. 3.1 freescale semiconductor 4-1 4 packaging 4.1 pin-out and package information this section provides information a bout the available package for this product, including diagrams of the package pinouts and tables describi ng how the signals described in section 2, ?signal/connection descriptions ? 1 are allocated for the package. the dsp 56366 is available in a 144-pin lqfp package. table 4-1 and table 4-2 show the pin/name assignments for the packages. 4.1.1 lqfp package description top view of the 144-pin lqfp package is shown in figure 4-1 with its pin-outs. th e package drawing is shown in figure 4-2 .
DSP56366 technical data, rev. 3.1 4-2 freescale semiconductor figure 4-1 144-pin package 108 d6 107 d5 106 d4 105 d3 104 gndd 103 vccd 102 d2 101 d1 100 d0 99 a17 98 a16 97 a15 96 gnda 95 vccqh 94 a14 93 a13 92 a12 91 vccql 90 gndq 89 a11 88 a10 87 gnda 86 vcca 85 a9 84 a8 83 a7 82 a6 81 gnda 80 vcca 79 a5 78 a4 77 a3 76 a2 75 gnda 74 vcca 73 a1 had4 37 vcch 38 gndh 39 had3 40 had2 41 had1 42 had0 43 reset# 44 vccp 45 pcap 46 gndp 47 sdo5_1/sdi0_1 48 vccqh 49 fst_1 50 aa2 51 cas# 52 sckt_1 53 gndq 54 extal 55 vccql 56 vccc 57 gndc 58 fsr_1 59 sckr_1 60 pinit/nmi# 61 ta# 62 br# 63 bb# 64 vccc 65 gndc 66 wr# 67 rd# 68 aa1 69 aa0 70 bg# 71 a0 72 sck/scl 1 ss#/ha2 2 hreq# 3 sdo0/sdo0_1 4 sdo1/sdo1_1 5 sdo2/sdi3/sdo2_1/sdi3_1 6 sdo3/sdi2/sdo3_1/sdi2_1 7 vccs 8 gnds 9 sdo4/sdi1 10 sdo5/sdi0 11 fst 12 fsr 13 sckt 14 sckr 15 hckt 16 hckr 17 vccql 18 gndq 19 vccqh 20 hds/hwr 21 hrw/hrd 22 hack/hrrq 23 horeq/htrq 24 vccs 25 gnds 26 ado 27 aci 28 tio0 29 hcs/ha10 30 ha9/ha2 31 ha8/ha1 32 has/ha0 33 had7 34 had6 35 had5 36 144 miso/sda 143 mosi/ha0 142 tms 141 tck 140 tdi 139 tdo 138 sdo4_1/sdi1_1 137 moda/irqa# 136 modb/irqb# 135 modcirqc# 134 modd/irqd# 133 d23 132 d22 131 d21 130 gndd 129 vccd 128 d20 127 gndq 126 vccql 125 d19 124 d18 123 d17 122 d16 121 d15 120 gndd 119 vccd 118 d14 117 d13 116 d12 115 d11 114 d10 113 d9 112 gndd 111 vccd 110 d8 109 d7
DSP56366 technical data, rev. 3.1 freescale semiconductor 4-3 table 4-1 signal identification by name signal name pin no. signal name pin no. signal name pin no. signal name pin no. a0 72 d9 113 gnds 9 sdo0/sdo0_1 4 a1 73 d10 114 gnds 26 sdo1/sdo1_1 5 a2 76 d11 115 ha8/ha1 32 sdo 2/sdi3/sdo2_1/sdi3_1 6 a3 77 d12 116 ha9/ha2 31 sdo 3/sdi2/sdo3_1/sdi2_1 7 a4 78 d13 117 hack/hrrq 23 sdo4/sdi1 10 a5 79 d14 118 had0 43 sdo4_1/sdi1_1 138 a6 82 d15 121 had1 42 sdo5/sdi0 11 a7 83 d16 122 had2 41 sdo5_1/sdi0_1 48 a8 84 d17 123 had3 40 ss#/ha2 2 a9 85 d18 124 had4 37 ta# 62 a10 88 d19 125 had5 36 tck 141 a11 89 d20 128 had6 35 tdi 140 a12 92 d21 131 had7 34 tdo 139 a13 93 d22 132 has/ha0 33 tio0 29 a14 94 d23 133 hckr 17 tms 142 a15 97 extal 55 hckt 16 vcca 74 a16 98 fsr 13 hcs/ha10 30 vcca 80 a17 99 fsr_1 59 hds/hwr 21 vcca 86 aa0 70 fst 12 horeq/htrq 24 vccc 57 aa1 69 fst_1 50 hreq# 3 vccc 65 aa2 51 gnda 75 hrw/hrd 22 vccd 103 aci 28 gnda 81 moda/irqa# 137 vccd 111 ado 27 gnda 87 modb/irqb# 136 vccd 119 bb# 64 gnda 96 modc/irqc# 135 vccd 129 bg# 71 gndc 58 modd/irqd# 134 vcch 38 br# 63 gndc 66 miso/sda 144 vccqh 20 cas# 52 gndd 104 mosi/ha0 143 vccqh 95 d0 100 gndd 112 pcap 46 vccqh 49 d1 101 gndd 120 pinit/nmi# 61 vccql 18 d2 102 gndd 130 rd# 68 vccql 56 d3 105 gndh 39 reset# 44 vccql 91 d4 106 gndp 47 sck/scl 1 vccql 126 d5 107 gndq 19 sckr 15 vccp 45 d6 108 gndq 54 sckr_1 60 vccs 8 d7 109 gndq 90 sckt 14 vccs 25 d8 110 gndq 127 sckt_1 53 wr# 67
DSP56366 technical data, rev. 3.1 4-4 freescale semiconductor table 4-2 signal identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1 sck/scl 37 had4 73 a1 109 d7 2 ss#/ha2 38 vcch 74 vcca 110 d8 3 hreq# 39 gndh 75 gnda 111 vccd 4 sdo0/sdo0_1 40 had3 76 a2 112 gndd 5 sdo1/sdo1_1 41 had2 77 a3 113 d9 6 sdo2/sdi3/sdo2_1/sdi3_1 42 had1 78 a4 114 d10 7 sdo3/sdi2/sdo3_1/sdi2_1 43 had0 79 a5 115 d11 8 vccs 44 reset# 80 vcca 116 d12 9 gnds 45 vccp 81 gnda 117 d13 10 sdo4/sdi1 46 pcap 82 a6 118 d14 11 sdo5/sdi0 47 gnd 83 a7 119 vccd 12 fst 48 sdo5_1/sdi0_1 84 a8 120 gndd 13 fsr 49 vccqh 85 a9 121 d15 14 sckt 50 fst_1 86 vcca 122 d16 15 sckr 51 aa2 87 gnda 123 d17 16 hckt 52 cas# 88 a10 124 d18 17 hckr 53 sckt_1 89 a11 125 d19 18 vccql 54 gndq 90 gndq 126 vccql 19 gndq 55 extal 91 vccql 127 gndq 20 vccqh 56 vccql 92 a12 128 d20 21 hds/hwr 57 vccc 93 a13 129 vccd 22 hrw/hrd 58 gndc 94 a14 130 gndd 23 hack/hrrq 59 fsr_1 95 vccqh 131 d21 24 horeq/htrq 60 sckr_1 96 gnda 132 d22 25 vccs 61 pinit/nmi# 97 a15 133 d23 26 gnds 62 ta# 98 a16 134 modd/irqd# 27 ado 63 br# 99 a17 135 modc/irqc# 28 aci 64 bb# 100 d0 136 modb/irqb# 29 tio0 65 vccc 101 d1 137 moda/irqa# 30 hcs/ha10 66 gndc 102 d2 138 sdo4_1/sdi1_1 31 ha9/ha2 67 wr# 103 vccd 139 tdo 32 ha8/ha1 68 rd# 104 gndd 140 tdi 33 has/ha0 69 aa1 105 d3 141 tck 34 had7 70 aa0 106 d4 142 tms 35 had6 71 bg# 107 d5 143 mosi/ha0 36 had5 72 a0 108 d6 144 miso/sda
DSP56366 technical data, rev. 3.1 freescale semiconductor 4-5 4.1.2 lqfp package mechanical drawing figure 4-2 DSP56366 144-pin lqfp package case 918-03
DSP56366 technical data, rev. 3.1 4-6 freescale semiconductor
DSP56366 technical data, rev. 3.1 freescale semiconductor 5-1 5 design considerations 5.1 thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the following equation: where: t a = ambient temperature c r qja = package junction-to-ambient thermal resistance c/w p d = power dissipation in package w historically, thermal resistance has been expressed as the sum of a ju nction-to-case thermal resistance and a case-to-ambient thermal resistance. where: r ja = package junction-to-ambie nt thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w r jc is device-related and ca nnot be influenced by the user. the user controls the ther mal environment to change the case-to-ambien t thermal resistance, r ca . for example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the pr inted circuit board (pcb), or otherwise change the thermal dissi pation capability of the area surr ounding the device on a pcb. this model is most useful for ceramic pa ckages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient envi ronment. for ceramic packages, in situations where the heat flow is split between a path to the case an d an alternate path through the pcb, analysis of the device thermal performance may need the additional modeling capabili ty of a system level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperature of the pcb to which the package is mounted. again, if the estimations obtained from r ja do not satisfactori ly answer whether the thermal performance is adequate, a sy stem level model may be appropriate. a complicating factor is the existence of three comm on ways for determining th e junction-to-case thermal resistance in plastic packages. ? to minimize temperature variation across the surface, the thermal resi stance is measured from the junction to the outside surface of the package (case) closest to th e chip mounting area when that surface has a proper heat sink. t j t a p d r ja () + = r ja r jc r ca + =
DSP56366 technical data, rev. 3.1 5-2 freescale semiconductor ? to define a value approximately equal to a j unction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. ? if the temperature of the package case (t t ) is determined by a thermoc ouple, the thermal resistance is computed using the valu e obtained by the equation (t j ? t t )/p d . as noted above, the junction-to-case th ermal resistances quoted in this da ta sheet are determined using the first definition. from a practical standpoint, that va lue is also suitable for determining the junction temperature from a case thermocoupl e reading in forced convection e nvironments. in natural convection, using the junction-to-case thermal resistance to es timate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slight ly hotter than actual temperature. hence, the new thermal metr ic, thermal characteri zation parameter or jt , has been defined to be (t j ? t t )/p d . this value gives a better estimate of the junction temp erature in natural convection when using the surface temperature of the package. remember that surface temperature readings of packages are subject to significant errors caused by in adequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. th e recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 5.2 electrical design considerations caution this device contains circuitry protecti ng against damage due to high static voltage or electrical fields. however, normal preca utions should be taken to avoid exceeding maximum voltage ra tings. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either gnd or v cc ). the suggested value for a pullup or pulldown resistor is 10 kohm. use the following list of recommendati ons to assure correct dsp operation: ? provide a low-impedanc e path from the board power supply to each v cc pin on the dsp and from the board ground to each gnd pin. ? use at least six 0.01?0.1 f bypass capacitors positioned as close as possible to the four sides of the package to connect the v cc power source to gnd. ? ensure that capacitor leads and associated prin ted circuit traces that connect to the chip v cc and gnd pins are less than 1.2 cm (0.5 inch) per capacitor lead. ? use at least a four-layer pc b with two inner layers for v cc and gnd. ? because the dsp output signals have fast rise and fall times, pcb trace lengths shoul d be minimal. this recommendation particularly applies to th e address and data buses as well as the irqa , irqb , irqc , irqd , ta and bg pins. maximum pcb trace lengths on the order of 15 cm (6 inches) are recommended. ? consider all device loads as we ll as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in systems with higher ca pacitive loads that could create higher transient currents in the v cc and gnd circuits. ? all inputs must be terminated (i .e., not allowed to float) using cm os levels, except for the three pins with internal pull-up resistors (tms, tdi, tck ).
DSP56366 technical data, rev. 3.1 freescale semiconductor 5-3 ? take special care to mini mize noise levels on the v ccp and gnd p pins. ? if multiple DSP56366 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. ?reset must be asserted when the chip is power ed up. a stable extal signal must be supplied while reset is being asserted. ? at power-up, ensure that the voltage difference between the 5 v tolerant pins and the chip v cc never exceeds 3.95 v. 5.3 power consumption considerations power dissipation is a key issue in portable dsp applications. some of the factors which affect current consumption are descri bed in this section. most of the current consumed by cm os devices is alternating current (ac), which is charging a nd discharging the capacitances of the pins and internal nodes. current consumption is descri bed by the following formula: where: c = node/pin capacitance v = voltage swing f = frequency of node/pin toggle the maximum internal current (i cci max) value reflects the typical possi ble switching of the internal buses on best-case operation conditions, which is not necessarily a real applic ation case. the typical internal current (i ccityp ) value reflects the average switching of the internal buses on typi cal operating conditions. for applications that require very lo w current consumption, do the following: ? set the ebd bit when not accessing external memory. ? minimize external memory accesses and use internal memory accesses. ? minimize the number of pins that are switching. ? minimize the capacitive load on the pins. ? connect the unused inputs to pull-up or pull-down resistors. ? disable unused peripherals. one way to evaluate power consum ption is to use a current per mips measurement methodology to minimize specific board effects (i.e., to compensate for measured board current not caused by the dsp). a benchmark power consumption te st algorithm is listed in appendix a . use the test algorithm, specific test current measurements, and the following e quation to derive the current per mips value. example 1. current consumption for a port a address pin loaded with 50 pf capacitance, operating at 3.3 v, and with a 120 mhz clock, toggling at its maximum possible rate (60 mhz), the current consumption is icv f = i5010 12 ? 3.3 60 10 6 9.9ma = =
DSP56366 technical data, rev. 3.1 5-4 freescale semiconductor where: i typf2 = current at f2 i typf1 = current at f1 f2 = high frequency (any speci fied operating frequency) f1 = low frequency (any specified ope rating frequency lower than f2) note f1 should be significantly less than f2. for example, f2 could be 66 mhz and f1 could be 33 mhz. the degree of difference between f1 and f2 determines the amount of precision with which the current rating can be determined for an application. 5.4 pll performance issues the following explanations should be considered as general observations on expected pll behavior. there is no testing that verifies these exact numbe rs. these observations were measured on a limited number of parts and were not verified over the entire temperature and voltage ranges. 5.4.1 phase jitter performance the phase jitter of the pll is defined as the variat ions in the skew between the falling edges of extal and the internal dsp clock for a given device in spec ific temperature, voltage , input frequency and mf. these variations are a result of the pll locking me chanism. for input frequencies greater than 15 mhz and mf 4, this jitter is less than 0.6 ns; otherwise, this jitter is not guaranteed. however, for mf < 10 and input frequencies greater than 10 mhz, this jitter is less than 2 ns. 5.4.2 frequency jitter performance the frequency jitter of the pll is defined as the variation of the frequency of the internal dsp clock. for small mf (mf < 10) this jitter is smaller than 0.5% . for mid-range mf (10 < mf < 500) this jitter is between 0.5% and approximately 2%. for large mf (mf > 500), the frequency jitter is 2?3%. 5.4.3 input (extal) jitter requirements the allowed jitter on the fre quency of extal is 0.5%. if the rate of change of the frequency of extal is slow (i.e., it does not jump be tween the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a l ong time), then the allowed jitter can be 2%. the phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values. imips ? imhz ? i ( typf2 i typf1 ) f2 f1 = () ? ? ==
DSP56366 technical data, rev. 3.1 freescale semiconductor 5-5 5.5 host port considerations careful synchronization is require d when reading multi-bit regist ers that are written by another asynchronous system. this synchron ization is a common problem wh en two asynchronous systems are connected, as they are in the host interface. the fo llowing paragraphs present considerations for proper operation. 5.5.1 host programming considerations ? unsynchronized reading of receive byte registers ?when reading the receive byte registers, receive register high (rxh), receive register middle (rxm), or receive register low (rxl), the host interface programmer shoul d use interrupts or poll the receive register da ta full (rxdf) flag that indicates whether data is ava ilable. this ensures that the data in the receive byte registers will be valid. ? overwriting transmit byte registers ?the host interface programmer should not write to the transmit byte registers, transmit register high (txh), transmit register middle (txm), or transmit register low (txl), unless the transmit register da ta empty (txde) bit is set, indicating that the transmit byte registers are empty. this ensures that the transmit byt e registers will transfer valid data to the host receive (hrx) register. ? synchronization of status bits from dsp to host ?hc, horeq , dma, hf3, hf2, trdy, txde, and rxdf status bits are set or cleared from inside the dsp and read by the host processor (refer to the user?s manual for desc riptions of these status bits). th e host can read these status bits very quickly without regard to the clock rate used by the dsp, but the state of the bit could be changing during the read operation. th is is not generally a system probl em, because the bit will be read correctly in the next pass of any host polling routine. however, if the host asserts hen for more than timing number 31, with a minimum cycle time of timing number 31 + 32, th en these status bits are guaranteed to be stable. exercise care when reading status bits hf3 and hf2 as an encoded pair. if the dsp changes hf3 and hf2 from 00 to 11, there is a smal l probability that the hos t could read the bits during the transition and receive 01 or 10 instead of 11. if the combinati on of hf3 and hf2 has significance, the host could read the wrong comb ination. therefore, read the bits twice and check for consensus. ? overwriting the host vector ?the host interface programmer should change the host vector (hv) register only when the host command (hc) bit is clear. this ensures that the dsp interrupt control logic will receive a stable vector. ? cancelling a pending host command exception ?the host processor may elect to clear the hc bit to cancel the host command exception request at any time before it is recognized by the dsp. because the host does not know exactly when the ex ception will be recognized (due to exception processing synchronization and pipeline delays), the dsp may execute the host command exception after the hc bit is cleared. for these reasons, the hv bits must not be changed at the same time that the hc bit is cleared. ? variance in the host interface timing ?the host interface (hdi) may vary (e.g. due to the pll lock time at reset). therefore, a host which attempts to load (boot strap) the dsp sh ould first make
DSP56366 technical data, rev. 3.1 5-6 freescale semiconductor sure that the part has completed its hi port pr ogramming (e.g., by setting the init bit in icr then polling it and waiting it to be cl eared, then reading the isr or by writing the treq/rreq together with the init and then polling init, isr, and the horeq pin). 5.5.2 dsp programming considerations ? synchronization of status bits from host to dsp ?dma, hf1, hf0, hcp, htde, and hrdf status bits are set or cleared by the host processor side of the inte rface. these bits are individually synchronized to the dsp clock. (refer to the user?s manual for descriptions of these status bits.) ? reading hf0 and hf1 as an encoded pair ?care must be exercised when reading status bits hf0 and hf1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have significance). a very small probability exists that the dsp will read the st atus bits synchronized during transition. therefore, hf0 and hf1 shoul d be read twice and checked for consensus.
DSP56366 technical data, rev. 3.1 freescale semiconductor 6-1 6 ordering information consult a freescale semiconductor, in c. sales office or authorized distributor to determine product availability and to place an order. for information on ordering dsp audio products, refe r to the current sg1004, dsp selector guide, at http://www.freescale.com
DSP56366 technical data, rev. 3.1 6-2 freescale semiconductor notes
DSP56366 technical data, rev. 3.1 freescale semiconductor a-1 appendix a power consumption benchmark the following benchmark program perm its evaluation of dsp power usage in a test situation. it enables the pll, disables the external cloc k, and uses repeated mu ltiply-accumulate instru ctions with a set of synthetic dsp application data to em ulate intensive sustained dsp operation. ;********************************************************************;********* *********************************************************** ;* ;* checks typical power consumption ;******************************************************************** page 200,55,0,0,0 nolist i_vec equ $000000 ; interrupt vectors for program debug only start equ $8000 ; main (external) program starting address int_prog equ $100 ; internal program memory starting address int_xdat equ $0 ; internal x-data memory starting address int_ydat equ $0 ; internal y-data memory starting address include "ioequ.asm" include "intequ.asm" list org p:start ; movep #$0123ff,x:m_bcr; bcr: area 3 : 1 w.s (sram) ; default: 1 w.s (sram) ; movep #$0d0000,x:m_pctl ; xtal disable ; pll enable ; clkout disable ; ; load the program ; move #int_prog,r0 move #prog_start,r1 do #(prog_end-prog_start),pload_loop move p:(r1)+,x0 move x0,p:(r0)+ nop pload_loop ; ; load the x-data ; move #int_xdat,r0
DSP56366 technical data, rev. 3.1 a-2 freescale semiconductor move #xdat_start,r1 do #(xdat_end-xdat_start),xload_loop move p:(r1)+,x0 move x0,x:(r0)+ xload_loop ; ; load the y-data ; move #int_ydat,r0 move #ydat_start,r1 do #(ydat_end-ydat_start),yload_loop move p:(r1)+,x0 move x0,y:(r0)+ yload_loop ; jmp int_prog prog_start move #$0,r0 move #$0,r4 move #$3f,m0 move #$3f,m4 ; clr a clr b move #$0,x0 move #$0,x1 move #$0,y0 move #$0,y1 bset #4,omr ; ebd ; sbr dor #60,_end mac x0,y0,a x:(r0)+,x1 y:(r4)+,y1 mac x1,y1,a x:(r0)+,x0 y:(r4)+,y0 add a,b mac x0,y0,a x:(r0)+,x1 mac x1,y1,a y:(r4)+,y0 move b1,x:$ff _end bra sbr nop nop nop nop prog_end nop nop xdat_start ; org x:0 dc $262eb9 dc $86f2fe dc $e56a5f
DSP56366 technical data, rev. 3.1 freescale semiconductor a-3 dc $616cac dc $8ffd75 dc $9210a dc $a06d7b dc $cea798 dc $8dfbf1 dc $a063d6 dc $6c6657 dc $c2a544 dc $a3662d dc $a4e762 dc $84f0f3 dc $e6f1b0 dc $b3829 dc $8bf7ae dc $63a94f dc $ef78dc dc $242de5 dc $a3e0ba dc $ebab6b dc $8726c8 dc $ca361 dc $2f6e86 dc $a57347 dc $4be774 dc $8f349d dc $a1ed12 dc $4bfce3 dc $ea26e0 dc $cd7d99 dc $4ba85e dc $27a43f dc $a8b10c dc $d3a55 dc $25ec6a dc $2a255b dc $a5f1f8 dc $2426d1 dc $ae6536 dc $cbbc37 dc $6235a4 dc $37f0d dc $63bec2 dc $a5e4d3 dc $8ce810 dc $3ff09 dc $60e50e dc $cffb2f dc $40753c dc $8262c5 dc $ca641a dc $eb3b4b dc $2da928 dc $ab6641 dc $28a7e6
DSP56366 technical data, rev. 3.1 a-4 freescale semiconductor dc $4e2127 dc $482fd4 dc $7257d dc $e53c72 dc $1a8c3 dc $e27540 xdat_end ydat_start ; org y:0 dc $5b6da dc $c3f70b dc $6a39e8 dc $81e801 dc $c666a6 dc $46f8e7 dc $aaec94 dc $24233d dc $802732 dc $2e3c83 dc $a43e00 dc $c2b639 dc $85a47e dc $abfddf dc $f3a2c dc $2d7cf5 dc $e16a8a dc $ecb8fb dc $4bed18 dc $43f371 dc $83a556 dc $e1e9d7 dc $aca2c4 dc $8135ad dc $2ce0e2 dc $8f2c73 dc $432730 dc $a87fa9 dc $4a292e dc $a63ccf dc $6ba65c dc $e06d65 dc $1aa3a dc $a1b6eb dc $48ac48 dc $ef7ae1 dc $6e3006 dc $62f6c7 dc $6064f4 dc $87e41d dc $cb2692 dc $2c3863 dc $c6bc60 dc $43a519 dc $6139de
DSP56366 technical data, rev. 3.1 freescale semiconductor a-5 dc $adf7bf dc $4b3e8c dc $6079d5 dc $e0f5ea dc $8230db dc $a3b778 dc $2bfe51 dc $e0a6b6 dc $68ffb7 dc $28f324 dc $8f2e8d dc $667842 dc $83e053 dc $a1fd90 dc $6b2689 dc $85b68e dc $622eaf dc $6162bc dc $e4a245 ydat_end
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